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TUSB3200CPAH 数据表(PDF) 68 Page - Texas Instruments |
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TUSB3200CPAH 数据表(HTML) 68 Page - Texas Instruments |
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68 / 93 page  A–20 A.5.1.5 USB Frame Number Register (Low Byte) (USBFNL – Address FFFBh) The USB frame number register (low byte) contains the least significant byte of the 11-bit frame number value received from the host PC in the start-of-frame packet. Bit 7 6 5 4 3 2 1 0 Mnemonic FN7 FN6 FN5 FN4 FN3 FN2 FN1 FN0 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 FN(7:0) Frame number The frame number bit values are updated by hardware each USB frame with the frame number field value received in the USB start-of-frame packet. The frame number can be used as a time stamp by the USB function. If the TUSB3200 frame timer is not locked to the host PC frame timer, then the frame number is incremented from the previous value when a pseudo start-of-frame occurs. A.5.1.6 USB Frame Number Register (High Byte) (USBFNH – Address FFFAh) The USB frame number register (high byte) contains the most significant 3 bits of the 11-bit frame number value received from the host PC in the start-of-frame packet. Bit 7 6 5 4 3 2 1 0 Mnemonic — — — — — FN10 FN9 FN8 Type R R R R R R R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:3 — Reserved Reserved for future use. 2:0 FN(10:8) Frame number The frame number bit values are updated by hardware each USB frame with the frame number field value received in the USB start-of-frame packet. The frame number can be used as a time stamp by the USB function. If the TUSB3200 frame timer is not locked to the host PC frame timer, then the frame number is incremented from the previous value when a pseudo start-of-frame occurs. A.5.2 DMA Registers This section describes the memory-mapped registers used for the four DMA channels. Each DMA channel has a set of three registers. A.5.2.1 DMA Channel 3 Time Slot Assignment Register (Low Byte) (DMATSL3 – Address FFF9h) The DMA channel 3 time slot assignment register (low byte) contains the eight least significant time slot bits. The time slot assignment bits are used to define which CODEC port interface time slots are supported by DMA channel 3. The DMA channel will control the transfer of data between the USB endpoint buffers and the CODEC port interface registers based on which bits are set. The direction of the data transfer depends on the value of the USB endpoint direction bit (EPDIR) in the DMA channel 3 control register. The desired time slot bits should be set by the MCU before the DMA channel is enabled. There are a total of fourteen time slot bits for each DMA channel. Bit 7 6 5 4 3 2 1 0 Mnemonic TSL7 TSL6 TSL5 TSL4 TSL3 TSL2 TSL1 TSL0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:0 TSL(7:0) Time slot assignment The DMA time slot assignment bits are set to a 1 by the MCU to define the CODEC port interface time slots supported by this DMA channel. |
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