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TUSB3200CPAH 数据表(PDF) 63 Page - Texas Instruments |
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TUSB3200CPAH 数据表(HTML) 63 Page - Texas Instruments |
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63 / 93 page  A–15 A.5 Memory-Mapped Registers The TUSB3200 device provides a set of control and status registers to be used by the MCU to control the overall operation of the device. This section describes the memory-mapped registers. Table A–3. Memory Mapped Registers Address Map ADDRESS MNEMONIC NAME FFFFh USBFADR USB function address register FFFEh USBSTA USB status register FFFDh USBIMSK USB interrupt mask register FFFCh USBCTL USB control register FFFBh USBFNL USB frame number register (low byte) FFFAh USBFNH USB frame number register (high byte) FFF9h DMATSL3 DMA channel 3 time slot assignment register (low byte) FFF8h DMATSH3 DMA channel 3 time slot assignment register (high byte) FFF7h DMACTL3 DMA channel 3 control register FFF6h DMATSL2 DMA channel 2 time slot assignment register (low byte) FFF5h DMATSH2 DMA channel 2 time slot assignment register (high byte) FFF4h DMACTL2 DMA channel 2 control register FFF3h Reserved Reserved for future use FFF2h Reserved Reserved for future use FFF1h Reserved Reserved for future use FFF0h DMATSL1 DMA channel 1 time slot assignment register (low byte) FFEFh DMATSH1 DMA channel 1 time slot assignment register (high byte) FFEEh DMACTL1 DMA channel 1 control register FFEDh Reserved Reserved for future use FFECh Reserved Reserved for future use FFEBh Reserved Reserved for future use FFEAh DMATSL0 DMA channel 0 time slot assignment register (low byte) FFE9h DMATSH0 DMA Channel 0 time slot assignment register (high byte) FFE8h DMACTL0 DMA channel 0 control register FFE7h ACGFRQ0 Adaptive clock generator frequency register (byte 0) FFE6h ACGFRQ1 Adaptive clock generator frequency register (byte 1) FFE5h ACGFRQ2 Adaptive clock generator frequency register (byte 2) FFE4h ACGCAPL Adaptive clock generator mclk capture register (low byte) FFE3h ACGCAPH Adaptive clock generator mclk capture register (high byte) FFE2h ACGDCTL Adaptive clock generator divider control register FFE1h ACGCTL Adaptive clock generator control register FFE0h CPTCNF1 CODEC port interface configuration register 1 FFDFh CPTCNF2 CODEC port interface configuration register 2 FFDEh CPTCNF3 CODEC port interface configuration register 3 FFDDh CPTCNF4 CODEC port interface configuration register 4 FFDCh CPTCTL CODEC port interface control and status register FFDBh CPTADR CODEC port interface address register FFDAh CPTDATL CODEC port interface data register (low byte) FFD9h CPTDATH CODEC port interface data register (high byte) FFD8h CPTVSLL CODEC port interface valid slots register (low byte) FFD7h CPTVSLH CODEC port interface valid slots register (high byte) |
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