TUSB3200CPAH datasheet(86/93 Pages) TI

86 / 93 page

A–38

A.5.5.4 I2C Interface Control and status register (I2CCTL – Address FFC0h)

The I2C interface control and status register contains various control and status bits used for the I2C interface

operation.

Bit

Mnemonic

RXF

RXIE

ERR

FRQ

TXE

TXIE

STPRD

STPWR

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

RXF

Receive data register full

The receive data register full bit is set to a 1 by hardware when a new data byte has

been received into the receive data register from the slave device. This bit is read

only and is cleared to a 0 by hardware when the MCU reads the new byte from the

receive data register. Note that when the MCU writes to the interrupt vector register,

the I2C receive data register full interrupt will be cleared but this status bit will not be

cleared at that time.

RXIE

Receive interrupt enable

The receive interrupt enable bit is set to a 1 by the MCU to enable the I2C receive

data register full interrupt.

ERR

Error condition

The error condition bit is set to a 1 by hardware when the slave device does not

respond. This bit is read/write and can only be cleared by the MCU.

FRQ

Frequency select

The frequency select bit is used by the MCU to program the I2C serial clock (SCL)

output signal frequency. A value of 0 sets the SCL frequency to 100 kHz and a value

of 1 sets the SCL frequency to 400 kHz.

TXE

Transmit data register empty

The transmit data register empty bit is set to a 1 by hardware when the data byte in

the transmit data register has been sent to the slave device. This bit is read only and

is cleared to a 0 by hardware when a new data byte is written to the transmit data

the I2C transmit data register empty interrupt will be cleared but this status bit will not

be cleared at that time.

TXIE

Transmit interrupt enable

The transmit interrupt enable bit is set to a 1 by the MCU to enable the I2C transmit

data register empty interrupt.

STPRD

Stop – read transaction

The stop read transaction bit is set to a 1 by the MCU to enable the hardware to

generate a stop condition on the I2C bus after the next data byte from the slave

device is received into the receive data register. The MCU should clear this bit to a 0

after the read transaction has concluded.

STPWR

Stop – write transaction

The stop write transaction bit is set to a 1 by the MCU to enable the hardware to

generate a stop condition on the I2C bus after the data byte in the transmit data

transaction has concluded.

TUSB3200CPAH 数据表(PDF) 86 Page - Texas Instruments

TUSB3200CPAH 数据表(HTML) 86 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

数据表下载