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TUSB3200CPAH 数据表(PDF) 44 Page - Texas Instruments |
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TUSB3200CPAH 数据表(HTML) 44 Page - Texas Instruments |
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44 / 93 page  3–4 3.4.3 CODEC Port Interface Signals (AC ’97 Modes), TA = 25°C, DVDD = 3.3 V, DVDSS = 5 V, AVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNITS fBIT_CLK Frequency, BIT_CLK See Note 1 12.288 MHz tcyc1 Cycle time, BIT_CLK See Note 1 81.4 ns tw1(H) Pulse duration, BIT_CLK high See Note 1 36 40.7 45 ns tw1(L) Pulse duration, BIT_CLK low See Note 1 36 40.7 45 ns fSYNC Frequency, SYNC CL = 50 pF 48 kHz tcyc2 Cycle time, SYNC CL = 50 pF 20.8 µs tw2(H) Pulse duration, SYNC high CL = 50 pF 1.3 µs tw2(L) Pulse duration, SYNC low CL = 50 pF 19.5 µs tpd1 Propagation delay time, BIT_CLK rising edge to SYNC, SD_OUT and RESET CL = 50 pF 15 ns tsu Setup time, SD_IN to BIT_CLK falling edge 10 ns th Hold time, SD_IN from BIT_CLK falling edge 10 ns NOTE 1: Worst case duty cycle is 45/55. tw1(H) tw1(L) tcyc1 tw2(H) tw2(L) tcyc2 BIT_CLK SYNC Figure 3–3. BIT_CLK and SYNC Timing Waveforms tsu th BIT_CLK tpd1 SYNC, SD_OUT, RESET SD_IN Figure 3–4. SYNC, SD_IN, and SD_OUT Timing Waveforms |
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