TUSB3200CPAH datasheet(58/93 Pages) TI

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A.4.3.6 USB Out Endpoint – Configuration Byte (OEPCNFx)

The USB out endpoint configuration byte contains the various bits used to configure and control the endpoint. Note

that the bits in this byte take on different functionality based on the type of endpoint defined. Basically, the control,

iInterrupt, and bulk endpoints function differently than the isochronous endpoints.

A.4.3.6.1 USB Out Endpoint – Control, Interrupt or Bulk configuration byte

This section defines the functionality of the bits in the USB out endpoint configuration byte for control, interrupt, and

bulk endpoints.

Bit

Mnemonic

OEPEN

ISO

TOGGLE

DBUF

STALL

OEPIE

—

Type

R/W

BIT

MNEMONIC

NAME

DESCRIPTION

OEPEN

Endpoint enable

The endpoint enable bit is set to a 1 by the MCU to enable the out endpoint.

ISO

Isochronous endpoint

The isochronous endpoint bit is set to a 1 by the MCU to specify the use of a

particular out endpoint for isochronous transactions. This bit should be cleared to a 0

by the MCU to use a particular out endpoint for control, interrupt or bulk transactions.

TOGGLE

Toggle

The toggle bit is controlled by the UBM and is toggled at the end of a successful out

data stage transaction if a valid data packet is received and the data packet PID

matches the expected PID.

DBUF

Double buffer mode

The double buffer mode bit is set to a 1 by the MCU to enable the use of both the X

and Y data packet buffers for USB transactions to a particular out endpoint. This bit

should be cleared to a 0 by the MCU to use the single buffer mode. In the single

buffer mode, only the X buffer is used.

STALL

Stall

The stall bit is set to a 1 by the MCU to stall endpoint transactions. When this bit is

set, the hardware will automatically return a stall handshake to the host PC for any

transaction received for the endpoint. An exception is the control endpoint setup

stage transaction, which must always be received. This requirement allows a

Clear_Feature_Stall request to be received from the host PC. Control endpoint data

and status stage transactions however can be stalled. The stall bit is cleared to a 0

by the MCU if a Clear_Feature_Stall request or a USB reset is received from the host

PC. For a control write transaction, if the amount of data received is greater than

expected, the UBM will set the stall bit to a 1 to stall the endpoint. When the stall bit is

set to a 1 by the UBM, the USB out endpoint 0 interrupt will be generated.

OEPIE

Interrupt enable

The interrupt enable bit is set to a 1 by the MCU to enable the out endpoint interrupt.

See section A.5.7.1 for details on the out endpoint interrupts.

1:0

—

Reserved

Reserved for future use

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