TUSB3200CPAH datasheet(17/93 Pages) TI

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2–1

2 Description

2.1

Architectural Overview

2.1.1

Oscillator and PLL

Using an external 6-MHz crystal, the TUSB3200 derives the fundamental 48-MHz internal clock signal using an

on-chip oscillator and PLL. Using the PLL output, the other required clock signals are generated by the clock

generator and adaptive clock generator.

2.1.2

Clock Generator and Sequencer Logic

Utilizing the 48-MHz input from the PLL, the clock generator logic generates all internal clock signals, except for the

CODEC port interface master clock (MCLK) and serial clock (CSCLK) signals. The TUSB3200 internal clocks include

the 48-MHz clock, a 24-MHz clock, a 12-MHz clock and a USB clock. The USB clock also has a frequency of 12-MHz.

The USB clock is the same as the 12-MHz clock when the TUSB3200 is transmitting data and is derived from the

data when the TUSB3200 is receiving data. To derive the USB clock when receiving USB data, the TUSB3200 utilizes

an internal digital PLL (DPLL) that uses the 48-MHz clock.

The sequencer logic controls the access to the SRAM used for the USB endpoint configuration blocks and the USB

endpoint buffer space. The SRAM can be accessed by the MCU, USB buffer manager (UBM) or DMA channels. The

sequencer controls the access to the memory using a round robin fixed priority arbitration scheme. This basically

means that the sequencer logic generates grant signals for the MCU, UBM and DMA channels at a predetermined

fixed frequency.

2.1.3

Adaptive Clock Generator (ACG)

The adaptive clock generator is used to generate a master clock output signal (MCLKO) to be used by the CODEC

port interface and the CODEC device. To synchronize the sample rate conversion of data by the CODEC to the USB

frame rate, the MCLKO signal generated by the adaptive clock generator must be used. The synchronization of the

MCLKO signal to the USB frame rate is controlled by the MCU by programming the adaptive clock generator

frequency value. The MCLKO frequency is monitored by the MCU and updated as required. For asynchronous

operation, an external source can be used to generate a master clock input signal (MCLKI) to be used by the CODEC

port interface. In this scenario, the CODEC device should also use the same master clock signal (MCLKI).

2.1.4

USB Transceiver

The TUSB3200 provides an integrated transceiver for the USB port. The transceiver includes a differential output

driver, a differential input receiver and two single ended input buffers. The transceiver connects to the USB DP and

DM signal terminals.

2.1.5

USB Serial Interface Engine (SIE)

The serial interface engine logic manages the USB packet protocol requirements for the packets being received and

transmitted on the USB by the TUSB3200 device. For packets being received, the SIE decodes the packet identifier

field (PID) to determine the type of packet being received and to ensure the PID is valid. For token packets and data

packets being received, the SIE calculates the packet cycle redundancy check (CRC) and compares the value to the

CRC contained in the packet to verify that the packet was not corrupted during transmission. For token packets and

data packets being transmitted, the SIE generates the CRC that is transmitted with the packet. For packets being

transmitted, the SIE also generates the synchronization field (SYNC) that is an eight bit filed at the beginning of each

packet. In addition, the SIE generates the correct PID for all packets being transmitted. Another major function of the

SIE is the overall serial-to-parallel conversion of the data packets being received and the parallel-to-serial conversion

of the data packets being transmitted.

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