TUSB3200CPAH datasheet(13/93 Pages) TI

13 / 93 page

1–7

1.6

Terminal Functions – Normal Mode (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

SDA

I/O

I2C interface serial data input/output: SDA is the bidirectional data signal for the I2C serial interface. This signal

uses a 3.3-V to 5-VTTL level shifting open drain output buffer and a 5-V to 3.3-V TTL level shifting input buffer.

TEST

Test mode enable: Input used to enable the device for the factory test mode. This signal uses a 3.3-V

TTL/LVCMOS input buffer.

XINT

External interrrupt: An active low input used by external circuitry to interrupt the on-chip 8052 MCU. This signal

uses a 5-V compatible input buffer.

XTALI

Crystal input: Input to the on-chip oscillator from an external 6-MHz crystal.

XTALO

Crystal Output: Output from the on-chip oscillator to an external 6-MHz crystal.

1.7

Terminal Functions – External MCU Mode

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AVDD

3.3-V Analog supply voltage

AVSS

Analog ground

CSCLK

I/O

CODEC port interface serial clock:CSCLK is the serial clock for the CODEC port interface used to clock the

CSYNC, CDATO, CDATI, CRESET AND CSCHNE signals. This signal uses a 5-V compatible TTL/LVCMOS

input/output buffer.

CSYNC

I/O

CODEC port interface frame sync: CSYNC is the frame synchronization signal for the CODEC port interface.

This signal uses a 5-V compatible TTL/LVCMOS input/output buffer.

CDATO

I/O

CODEC port interface serial data output: See section 1.9 for details. This signal uses a 5-V compatible TTL/

LVCMOS input/output buffer.

CDATI

I/O

CODEC port interface serial data input: See section 1.9 for details. This signal uses a 5-V compatible TTL/

LVCMOS input/output buffer.

CRESET

I/O

CODEC port interface reset output: See section 1.9 for details. This signal uses a 5-V compatible TTL/

LVCMOS input/output buffer.

CSCHNE

I/O

CODEC port interface secondary channel enable: See section 1.9 for details. This signal uses a 5-V

compatible TTL/LVCMOS input/output buffer.

I/O

USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair used to

connect the TUSB3200 device to the universal serial bus.

I/O

USB differential pair data signal minus: DM is the negative signal of the bidirectional USB differential pair used

to connect the TUSB3200 device to the universal serial bus.

DVDD

9, 21, 37

3.3-V Digital supply voltage

DVDDS

27, 43

5 V-Digital supply voltage

DVSS

5, 16, 33,

Digital ground

EXTEN

External MCU mode enable: Input used to enable the device for the external MCU mode. This signal uses a 3.3

V TTL/LVCMOS input buffer.

MCLKI

Master clock input: An input that can be used as the master clock for the CODEC port interface or the source for

MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.

MCLKI2

Master clock input 2: An input that can be used as the master clock for the CODEC port interface or the source

for MCLKO2. This signal uses a 5-V to 3.3-V level shifting input buffer.

MCLKO

Master clock output: The output of the ACG that can be used as the master clock for the CODEC port interface

and the CODEC. This signal uses a 3.3-V TTL/LVCMOS output buffer

MCLKO2

Master clock output 2: An output that can be used as the master clock for the CODEC port interface and the

CODEC. This clock signal can also be used as a miscellaneous clock. This signal uses a 3.3-V TTL/LVCMOS

output buffer.

MCUAD0

I/O

MCU multiplexed address/data bit 0: Multiplexed address bit 0/data bit 0 for external MCU access to the

TUSB3200 external data memory space.

TUSB3200CPAH 数据表(PDF) 13 Page - Texas Instruments

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