TUSB3200CPAH datasheet(26/93 Pages) TI

26 / 93 page

2–10

Data Stage Transaction(s):

The data packet to be sent to the host PC is written to the in endpoint 0 buffer by the MCU. The MCU also

updates the data count value then clears the in endpoint 0 NACK bit to a 0 to enable the data packet to be

sent to the host PC.

The host PC sends an in token packet addressed to the in endpoint 0. After receiving the in token, the UBM

transmits the data packet to the host PC. IF the data packet is received without errors by the host PC, then

an ACK handshake is returned. The UBM will then toggle the TOGGLE bit, set the NACK bit to a 1 and assert

the endpoint interrupt.

The MCU services the interrupt and prepares to send the next data packet to the host PC.

If the NACK bit is set to a 1 when the in token packet is received, the UBM simply returns a NAK handshake

to the host PC. IF the STALL bit is set to a 1 when the in token packet is received, the UBM simply returns

a STALL handshake to the host PC. If a no handshake packet is received from the host PC, then the UBM

prepares to retransmit the same data packet again.

MCU continues to send data packets until all data has been sent to the host PC.

Status Stage Transaction:

For out endpoint 0, the MCU sets the TOGGLE bit to 1, then clears the NACK bit to a 0 to enable the data

packet to be sent to the host PC. Note that for a status stage transaction a null data packet with a DATA1

PID is sent to the host PC.

The host PC sends an out token packet addressed to out endpoint 0. If the data packet is received without

an error then the UBM will update the data count value, toggle the TOGGLE bit, set the NACK bit to a 1,

return an ACK handshake to the host PC and assert the endpoint interrupt.

The MCU services the interrupt. If the status stage transaction completed successfully, then the MCU

should clear the interrupt and clear the NACK bit.

If the NACK bit is set to a 1 when the in data packet is received, the UBM simply returns a NAK handshake

to the host PC. If the STALL bit is set to a 1 when the in data packet is received, the UBM simply returns

a STALL handshake to the host PC. If a CRC or bit stuff error occurs when the data packet is received, then

no handshake is returned to the host PC.

2.2.7.2 Interrupt Transfers

The TUSB3200 supports interrupt data transfers both to and from the host PC. Devices that need to send or receive

a small amount of data with a specified service period should use the interrupt transfer type. In endpoints 1 through

7 and out endpoints 1 through 7 can all be configured as interrupt endpoints.

2.2.7.2.1 Interrupt Out Transaction

The steps to be followed for an interrupt out transaction are as follows:

MCU initializes one of the out endpoints as an out interrupt endpoint by programming the appropriate USB

endpoint configuration block. This entails programming the buffer size and buffer base address, selecting

the buffer mode, enabling the endpoint interrupt, initializing the toggle bit, enabling the endpoint, and

clearing the NACK bit.

The host PC sends an out token packet followed by a data packet addressed to the out endpoint. If the data

is received without an error then the UBM will write the data to the endpoint buffer, update the data count

value, toggle the toggle bit, set the NACK bit to a 1, return an ACK handshake to the host PC and assert

the endpoint interrupt.

The MCU services the interrupt and reads the data packet from the buffer. To read the data packet, the MCU

first needs to obtain the data count value. After reading the data packet, the MCU should clear the interrupt

and clear the NACK bit to allow the reception of the next data packet from the host PC.

TUSB3200CPAH 数据表(PDF) 26 Page - Texas Instruments

TUSB3200CPAH 数据表(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

数据表下载