TUSB3200CPAH datasheet(84/93 Pages) TI

84 / 93 page

A–36

A.5.4.10 CODEC Port Interface Valid Time Slots Register (High Byte) (CPTVSLH – Address FFD7h)

The CODEC port interface valid time slots register (high byte) contains the control bits used to specify which time

slots in the audio frame contain valid data. In addition the valid frame, primary CODEC ready and secondary CODEC

ready bits are contained in this register. This register is only used in the AC ’97 modes of operation.

Bit

Mnemonic

PCRDY

SCRDY

VTSL3

VTSL4

VTSL5

VTSL6

VTSL7

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

Valid frame

The valid frame bit is set to a 1 by the MCU to indicate that the current audio frame

contains at least one time slot with valid data. The MCU should clear this bit to a 0 to

indicate that the current audio frame does not contain any time slots with valid data.

PCRDY

Primary CODEC ready

The primary CODEC ready bit is updated by hardware each audio frame based on

the value of bit 15 in time slot 0 of the incoming serial data from the primary CODEC.

This bit is set to a 1 to indicate the primary CODEC is ready for operation.

SCRDY

Secondary CODEC ready

The secondary CODEC ready bit is updated by hardware each audio frame based

on the value of bit 15 in time slot 0 of the incoming serial data from the secondary

CODEC. This bit is set to a 1 to indicate the secondary CODEC is ready for

operation. Note that this bit is only used if a secondary CODEC is connected to the

TUSB3200 device.

4:0

VTSL(3:7)

Valid time slot

The valid time slot bits are set to a 1 by the MCU to define which time slots in the

audio frame contain valid data. The MCU should clear to a 0 the bits corresponding

to time slots that do not contain valid data. Note that bits 4 to 0 of this register

correspond to time slots 3 to 7.

A.5.5

I2C Interface Registers

This section describes the memory-mapped registers used for the I2C Interface control and operation. The I2C

iInterface has a set of four registers. See section 2.2.17 for the operation details of the I2C Interface.

A.5.5.1 I2C Interface Address Register (I2CADR – Address FFC3h)

The I2C interface address register contains the 7-bit I2C slave device address and the read/write transaction control

bit.

Bit

Mnemonic

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

7:1

A(6:0)

Address

The address bit values are set by the MCU to program the 7-bit I2C slave address of

the device to be accessed. Each I2C slave device should have a unique address on

the I2C bus. This address is used to identify the device on the bus to be accessed

and is not the internal memory address to be accessed within the device.

Read/w3rite control

The read/write control bit value is set by the MCU to program the type of I2C

transaction to be done. This bit should be set to a 1 by the MCU for a read transaction

and cleared to a 0 by the MCU for a write transaction.

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