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TUSB3200CPAH 数据表(PDF) 77 Page - Texas Instruments |
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TUSB3200CPAH 数据表(HTML) 77 Page - Texas Instruments |
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77 / 93 page  A–29 A.5.3.7 Adaptive Clock Generator Control Register (ACGCTL – Address FFE1h) The adaptive clock generator control register is used to store various control bits for the adaptive clock generator. Bit 7 6 5 4 3 2 1 0 Mnemonic — MCLKEN MCLKCP MCLKIS — DIVEN — — Type R R/W R/W R/W R R/W R R Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7 — Reserved Reserved for future use 6 MCLKEN MCLK output enable The MCLK output enable bit is set to a 1 by the MCU to enable the MCLKO signal to be an output from the TUSB3200 device. If the MCLKO signal is not being used, then the MCU can clear this bit to a 0 to disable the output. 5 MCLKCP MCLK capture source The MCLK capture source bit is used by the MCU to select between the MCLKO output signal and the MCLKO2 output signal as the source for the 16-bit MCLK cycle counter clock. When this bit is cleared to a 0, the clock used is MCLKO and when this bit is set to a 1 the clock used is MCLKO2. 4 MCLKIS MCLK input select The MCLK input select bit is used by the MCU to select between the MCLKI input signal and the MCLKI2 input signal as a source for MCLK if the internally generated MCLK is not being used. When this bit is cleared to a 0, the clock used is MCLKI and when this bit is set to a 1 the clock used is MCLKI2. 3 — Reserved Reserved for future use 2 DIVEN Divider enable The divider enable bit is set to a 1 by the MCU to enable the divide-by-I and divide-by-M circuits. The MCU should program the MCLK input select bit, the MCLK capture source bit and the MCLK output enable bit before setting this bit to a 1. 1:0 — Reserved Reserved for future use A.5.4 CODEC Port Interface Registers This section describes the memory-mapped registers used for the CODEC port interface control and operation. The codec port interface has a set of ten registers. Note that the four CODEC port interface configuration registers can only be written to by the MCU if the CODEC port enable bit (CPTEN) in the global control register is a 0. A.5.4.1 CODEC Port Interface Configuration Register 1 (CPTCNF1 – Address FFE0h) The CODEC port interface configuration register 1 is used to store various control bits for the CODEC port interface operation. Bit 7 6 5 4 3 2 1 0 Mnemonic NTSL4 NTSL3 NTSL2 NTSL1 NTSL0 MODE2 MODE1 MODE0 Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BIT MNEMONIC NAME DESCRIPTION 7:3 NTSL(4:0) Number of time slots The number of time slots bits are set by the MCU to program the number of time slots per audio frame. 00000b = 1 time slot per frame, 00001b = 2 time slots per frame, …, 11111b = 32 time slots per frame 2:0 MODE(2:0) Mode select The mode select bits are set by the MCU to program the CODEC port interface mode of operation. In addition to selecting the desired mode of operation, the MCU must also program the other configuration registers to obtain the correct serial interface format. 000b = mode 0 - General purpose mode 001b = mode 1 - AIC mode 010b = mode 2 - AC ’97 1.X mode 011b = mode 3 - AC ’97 2.X mode 100b = mode 4 - I2S mode – 3 serial data outputs and 1 serial data input 101b = mode 5 - I2S mode – 2 serial data outputs and 2 serial data inputs 110b = mode 6 - I2S mode – 1 serial data output and 3 serial data inputs 111b = mode 7 - I2S mode – 4 serial data outputs and no serial data inputs |
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