TUSB3200CPAH datasheet(81/93 Pages) TI

81 / 93 page

A–33

A.5.4.5 CODEC Port Interface Control and Status Register (CPTCTL – Address FFDCh)

The CODEC port interface control and status register contains various control and status bits used for the CODEC

port interface operation.

Bit

Mnemonic

RXF

RXIE

TXE

TXIE

—

CID1

CID0

CRST

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

RXF

Receive data register full

The receive data register full bit is set to a 1 by hardware when a new data value has

been received into the receive data register from the CODEC device. This bit is read

only and is cleared to a 0 by hardware when the MCU reads the new value from the

receive data register. Note that when the MCU writes to the interrupt vector register,

the CODEC port interface receive data register full interrupt will be cleared but this

status bit will not be cleared at that time.

RXIE

Receive interrupt enable

The receive interrupt enable bit is set to a 1 by the MCU to enable the C-port receive

data register full interrupt.

TXE

Transmit data register empty

The transmit data register empty bit is set to a 1 by hardware when the data value in

the transmit data register has been sent to the CODEC device. This bit is read only

and is cleared to a 0 by hardware when a new data byte is written to the transmit data

the CODEC port interface transmit data register empty interrupt will be cleared but

this status bit will not be cleared at that time.

TXIE

Transmit interrupt enable

The transmit interrupt enable bit is set to a 1 by the MCU to enable the CODEC port

interface transmit data register empty interrupt.

—

Reserved

Reserved for future use.

2:1

CID(1:0)

CODEC ID

The CODEC ID bits are used by the MCU to select between the primary CODEC

device and the secondary CODEC device for secondary communication in the AC

’97 modes of operation. When the bits are cleared to 00, the primary CODEC device

is selected. When the bits are set to 01, 10 or 11, the secondary CODEC device is

selected. Note that when only a primary CODEC device is connected to the

TUSB3200, the bits should remain cleared to 00.

CRST

CODEC reset

The CODEC reset bit is used by the MCU to control the CODEC port interface reset

(CRESET) output signal from the TUSB3200 device. When this bit is set to a 1, the

CRESET signal is a high. When this bit is cleared to a 0, the CRESET signal is active

low. At power up this bit is cleared to a 0, which means the CRESET output signal will

be active low and will remain active low until the MCU sets this bit to a 1. Note that

this output signal is not used in the I2S modes of operation.

TUSB3200CPAH 数据表(PDF) 81 Page - Texas Instruments

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