TUSB3200CPAH datasheet(66/93 Pages) TI

66 / 93 page

A–18

A.5.1.2 USB Status Register (USBSTA – Address FFFEh)

The USB status register contains various status bits used for USB operations.

Bit

Mnemonic

RSTR

SUSR

RESR

SOF

PSOF

SETUP

—

STPOW

Type

Default

BIT

MNEMONIC

NAME

DESCRIPTION

RSTR

Function reset

The function reset bit is set to a 1 by hardware in response to the host PC initiating a

USB reset to the function. When a USB reset occurs, all of the USB logic blocks,

including the SIE, UBM, frame timer, and suspend/resume are automatically reset.

The function reset enable (FRSTE) control bit in the USB control register can be

used to enable the USB reset to reset all TUSB3200 logic, except the shadow the

ROM (SDW) and the USB function connect (CONT) bits. When the FRSTE control

bit is set to a 1, the reset output (RSTO) signal from the TUSB3200 device will also

be active when a USB reset occurs. This bit is read only and is cleared when the

MCU writes to the interrupt vector register.

SUSR

Function suspend

The function suspend bit is set to a 1 by hardware when a USB suspend condition is

detected by the suspend/resume logic. See eection 2.2.5 for details on the USB

suspend and resume operation. This bit is read only and is cleared when the MCU

writes to the interrupt vector register.

RESR

Function resume

The function resume bit is set to a 1 by hardware when a USB resume condition is

detected by the suspend/resume logic. See section 2.2.5 for details on the USB

suspend and resume operation. This bit is read only and is cleared when the MCU

writes to the interrupt vector register.

SOF

Start-of-frame

The start-of-frame bit is set to a 1 by hardware when a new USB frame starts. This bit

is set when the SOF packet from the host PC is detected, even if the TUSB3200

frame timer is not locked to the host PC frame timer. This bit is read only and is

cleared when the MCU writes to the interrupt vector register. The nominal SOF rate

is 1 ms.

PSOF

Pseudo start-of-frame

The pseudo start-of-frame bit is set to a 1 by hardware when a USB pseudo SOF

occurs. The pseudo SOF is an artificial SOF signal that is generated when the

TUSB3200 frame timer is not locked to the host PC frame timer. This bit is read only

and is cleared when the MCU writes to the interrupt vector register. The nominal

pseudo SOF rate is 1 ms.

SETUP

Setup stage transaction

The setup stage transaction bit is set to a 1 by hardware when a successful control

endpoint setup stage transaction is completed. Upon completion of the setup stage

transaction, the USB control endpoint setup stage data packet buffer should contain

a new setup stage data packet.

—

Reserved

Reserved for future use

STPOW

Setup stage transaction over-

write

The setup stage transaction over-write bit is set to a 1 by hardware when the data in

the USB control endpoint setup data packet buffer is over-written. This scenario

occurs when the host PC prematurely terminates a USB control transfer by simply

starting a new control transfer with a new setup stage transaction.

TUSB3200CPAH 数据表(PDF) 66 Page - Texas Instruments

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