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TUSB3200CPAH 数据表(PDF) 23 Page - Texas Instruments |
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TUSB3200CPAH 数据表(HTML) 23 Page - Texas Instruments |
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23 / 93 page ![]() 2–7 3.3-V power supplies should start ramping from 0 volts and reach 95 percent of the final voltage values within 25 ms of each other. The turnoff requirement is that the 5-V and 3.3-V power supplies should start ramping from the steady-state voltage and reach 5 percent of these values within 25 ms of each other. In addition, the difference between the two voltages should never exceed 3.6-V while turning on or off. Normally, in a mixed voltage system, the 3.3-V supply is generated from a voltage regulator running from the 5-V supply. A voltage regulator, such as the Texas Instrument’s TP7133, can be used to meet these power sequencing requirements. 2.2.7 USB Transfers The TUSB3200 device supports all the USB data transfer types, which are control, bulk, interrupt, and isochronous. In accordance with the USB specification, endpoint zero is reserved for the control endpoint and is bidirectional. In addition to the control endpoint, the TUSB3200 is capable of supporting up to 7 in endpoints and 7 out endpoints. These additional endpoints can be configured as bulk, interrupt, or isochronous endpoints. The MCU handles all control, bulk, and interrupt endpoint transactions. In addition the MCU can handle isochronous endpoint transactions, such as a rate feedback endpoint to the host PC. However, for streaming isochronous data between the host PC and the CODEC interface port, the DMA channels are provided. 2.2.7.1 Controls Transfers Control transfers are used for configuration, command, and status communication between the host PC and the TUSB3200 device. Control transfers to the TUSB3200 device use in endpoint 0 and out endpoint 0. The three types of control transfers are control write, control write with no data stage, and control read. Note that the control endpoint must be initialized before connecting the TUSB3200 device to the USB. 2.2.7.1.1 Control Write Transfer (Out Transfer) The host PC uses a control write transfer to write data to the USB function. A control write transfer consists of a setup stage transaction, at least one out data stage transaction, and an in status stage transaction. The steps to be followed for a control write transfer are as follows: 1. MCU initializes in endpoint 0 and out endpoint 0 by programming the appropriate USB endpoint configuration blocks. This entails programming the buffer size and buffer base address, selecting the buffer mode, enabling the endpoint interrupt, initializing the TOGGLE bit, enabling the endpoint, and clearing the NACK bit for both in endpoint 0 and out endpoint 0. Setup Stage Transaction: 2. The host PC sends a setup token packet followed by the setup data packet addressed to out endpoint 0. If the data is received without an error, then the UBM will write the data to the setup data packet buffer, set the setup stage transaction (SETUP) bit to a 1 in the USB status register, return an ACK handshake to the host PC, and assert the setup stage transaction interrupt. Note that as long as the setup transaction (SETUP) bit is set to a 1, the UBM will return a NAK handshake for any data stage or status stage transactions regardless of the endpoint 0 NACK or STALL bit values. 3. The MCU services the interrupt and reads the setup data packet from the buffer then decodes the command. If the command is not supported or valid, the MCU should set the STALL bit in the out endpoint 0 configuration byte and the in endpoint 0 configuration byte before clearing the setup stage transaction (SETUP) bit. This will cause the device to return a STALL handshake for any data stage or status stage transactions. After reading the data packet and decoding the command, the MCU should clear the interrupt, which will automatically clear the setup stage transaction status bit. The MCU should also set the TOGGLE bit in the out endpoint 0 configuration byte to a 1. For control write transfers, the PID used by the host for the first out data packet will be a DATA1 PID and the TOGGLE bit must match. |
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