TUSB3200CPAH datasheet(78/93 Pages) TI

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A.5.4.2 CODEC Port Interface Configuration Register 2 (CPTCNF2 – Address FFDFh)

The CODEC port interface configuration register 2 is used to store various control bits for the CODEC port interface

operation.

Bit

Mnemonic

TSL0L1

TSL0L0

BPTSL2

BPTSL1

BPTSL0

TSLL2

TSLL1

TSLL0

Type

R/W

Default

BIT

MNEMONIC

NAME

DESCRIPTION

7:6

TSL0L(1:0)

Time slot 0 length

The time slot 0 Length bits are set by the MCU to program the number of serial clock

(CSCLK) cycles for time slot 0.

00b = CSCLK cycles for time slot 0 same as other time slots

01b = 8 CSCLK cycles for time slot 0

10b = 16 CSCLK cycles for time slot 0

11b = 32 CSCLK cycles for time slot 0

5:3

BPTSL(2:0)

Data bits per time slot

The data bits per time slot bits are set by the MCU to program the number of data bits

per audio time slot. Note that this value in not used for the secondary communication

address and data time slots.

000b = 8 data bits per time slot

001b = 16 data bits per time slot

010b = 18 data bits per time slot

011b = 20 data bits per time slot

100b = 24 data bits per time slot

101b = 32 data bits per time slot

110b = reserved

111b = reserved

2:0

TSLL(2:0)

Time slot length

The time slot length bits are set by the MCU to program the number of serial clock

(CSCLK) cycles for all time slots except time slot 0.

000b = 8 CSCLK cycles per time slot

001b = 16 CSCLK cycles per time slot

010b = 18 CSCLK cycles per time slot

011b = 20 CSCLK cycles per time slot

100b = 24 CSCLK cycles per time slot

101b = 32 CSCLK cycles per time slot

110b = reserved

111b = reserved

TUSB3200CPAH 数据表(PDF) 78 Page - Texas Instruments

TUSB3200CPAH 数据表(HTML) 78 Page - Texas Instruments

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