TUSB3200CPAH datasheet(30/93 Pages) TI

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2–14

The MCU reads the X (or Y) buffer data count byte to verify that the NACK bit is set and to obtain the sample

count in the new data packet. Note that if a new data packet has not been received, the NACK bit will not

be set. If there is a valid data packet in the buffer, then the MCU clears the NACK bit and proceeds with

reading the data.

2.2.7.4.3 Isochronous In Transaction (CODEC as source and host PC as destination)

The steps to be followed for an isochronous in transaction are as follows:

MCU initializes one of the in endpoints as an in isochronous endpoint by programming the appropriate USB

endpoint configuration block. This entails programming the buffer size and the buffer base address for both

the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint bit, enabling the

endpoint, and setting the NACK bit.

The MCU initializes one of the four DMA channels to support the isochronous in endpoint by programming

the appropriate DMA configuration registers.

During the current USB frame, the DMA proceeds with reading the data from the CODEC port interface and

storing the data in the X (or Y) endpoint buffer. At the end of the current USB frame, the DMA updates the

sample count in the data count byte then clears the X (or Y) buffer NACK bit to a 0. If a buffer overflow occurs,

the DMA will set the overflow bit in the endpoint configuration byte.

The host PC sends an iIn token packet addressed to the in endpoint. The UBM reads the X (or Y) buffer

data count byte to verify the NACK bit is cleared and to obtain the sample count of the new data packet.

The UBM reads the data packet from the X (or Y) endpoint buffer then transmits the data to the PC. At the

end of the USB transaction, the UBM sets the X (or Y) buffer NACK bit to a 1. Note that if a new data packet

has not been written to the buffer by the DMA, then the NACK bit will still be set to a 1 and the UBM will send

a null packet to the PC. Also, note that there is not an endpoint interrupt generated for isochronous

endpoints.

2.2.7.4.4 Isochronous In Transaction (MCU as source and host PC as destination)

The steps to be followed for an isochronous in transaction are as follows:

MCU initializes one of the in endpoints as an in isochronous endpoint by programming the appropriate USB

endpoint configuration block. This entails programming the buffer size and the buffer base address for both

the X and Y buffers and the bytes per sample bits, setting the isochronous endpoint bit, enabling the

endpoint, and setting the NACK bit.

The host PC sends an in token packet addressed to the in endpoint. The UBM reads the X (or Y) buffer data

count byte to verify the NACK bit is cleared and to obtain the sample count of the new data packet. The UBM

reads the data packet from the X (or Y) endpoint buffer then transmits the data to the PC. At the end of the

USB transaction, the UBM sets the X (or Y) buffer NACK bit to a 1. Note that if a new data packet has not

been written to the buffer by the MCU then the NACK bit will still be set to a 1 and the UBM will send a null

packet to the PC. Also, note that there is not an endpoint interrupt generated for isochronous endpoints.

2.2.8

Adaptive Clock Generator (ACG)

The adaptive clock generator is used to generate a programmable master clock output signal (MCLKO) that can be

used by the CODEC port interface and the CODEC device. The ACG can be used to generate the master clock for

the CODEC for USB asynchronous, synchronous, and adaptive modes of operation. However, for the USB

asynchronous mode of operation, an external clock can be used to drive the MCLKI signal of the TUSB3200. In this

scenario, the MCLKI signal would be used as the clock source for the CODEC port interface instead of the clock output

from the ACG.

A block diagram of the adaptive clock generator is shown in Figure 2–1. The frequency synthesizer circuit generates

a programmable clock with a frequency range of 12–25 MHz. The output of the frequency synthesizer feeds the

divide-by-M circuit, which can be programmed to divide by 1 to 16. As a result, the frequency range of the MCLKO

signal is 750 kHz to 25 MHz. The duty cycle of the MCLKO signal is 50% for all programmable MCLKO frequencies.

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