SIO1007 datasheet(21/108 Pages) MICROCHIP

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DS00002020A-page 21

SIO1007

9.0

SERIAL PORT (UART)

The SIO1007 incorporates one 8-pin 16C550A compatible UART. In addition, the SIO1007 provides an second UART

supporting a Serial Infrared Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp

and other PDAs), as well as Consumer IR. See Section 10.0, for description of Infrared Interface.

The SIO1007 incorporates two full function UARTs. They are compatible with the 16450, the 16450 ACE registers and

the 16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to-serial conversion

on transmit characters. The data rates are independently programmable from 460.8K baud down to 50 baud. The char-

acter options are programmable for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts.

The UARTs each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a

number from 1 to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration Reg-

isters for information on disabling, power down and changing the base address of the UARTs. The interrupt from a UART

is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic "0" disables that UART's interrupt.

The second UART also supports IrDA 1.2 (4Mbps), HP-SIR, ASK-IR and Consumer IR infrared modes of operation.

9.1

Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial ports are

defined by the configuration registers (see Configuration section). The Serial Port registers are located at sequentially

increasing addresses above these base addresses. The SIO1007 contains two serial ports, each of which contain a

Note 9-1

DLAB is Bit 7 of the Line Control Register

The following section describes the operation of the registers.

9.1.1

RECEIVE BUFFER REGISTER (RB)

Address Offset = 0H, DLAB = 0, READ ONLY

This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted and received

first. Received data is double buffered; this uses an additional shift register to receive the serial data stream and convert

it to a parallel 8 bit word which is transferred to the Receive Buffer register. The shift register is not accessible.

9.1.2

TRANSMIT BUFFER REGISTER (TB)

Address Offset = 0H, DLAB = 0, WRITE ONLY

This register contains the data byte to be transmitted. The transmit buffer is double buffered, utilizing an additional shift

register (not accessible) to convert the 8 bit data word to a serial format. This shift register is loaded from the Transmit

Buffer when the transmission of the previous byte is complete.

TABLE 9-1:

ADDRESSING THE SERIAL PORT

DLAB

(Note 9-1)

Receive Buffer (read)

Transmit Buffer (write)

Interrupt Enable (read/write)

Interrupt Identification (read)

FIFO Control (write)

Line Control (read/write)

Modem Control (read/write)

Line Status (read/write)

Modem Status (read/write)

Scratchpad (read/write)

Divisor LSB (read/write)

Divisor MSB (read/write

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