SIO1007 datasheet(16/108 Pages) MICROCHIP

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SIO1007

DS00002020A-page 16

 2005 - 2015 Microchip Technology Inc.

See the Low Pin Count (LPC) Interface Specification Reference, Section 5.2, for the sequence of cycles for the I/O Read

and Write cycles.

DMA Read and Write Cycles

DMA read cycles involve the transfer of data from the host (main memory) to the SIO1007. DMA write cycles involve

the transfer of data from the SIO1007 to the host (main memory). Data will be coming from or going to a FIFO and will

have minimal Sync times. Data transfers to/from the SIO1007 are 1 byte.

See the Low Pin Count (LPC) Interface Specification Reference, Section 6.4, for the field definitions and the sequence

of the DMA Read and Write cycles.

DMA Protocol

DMA on the LPC bus is handled through the use of the LDRQ# lines from the SIO1007 and special encodings on

LAD[3:0] from the host.

The DMA mechanism for the LPC bus is described in the Low Pin Count (LPC) Specification Revision 1.0.

7.1.1

POWER MANAGEMENT

CLOCKRUN Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 8.1.

LPCPD Protocol

The SIO1007 will function properly if the nLPCPD signal goes active and then inactive again without nPCI_RESET

becoming active. This is a requirement for notebook power management functions.

Although the LPC Bus spec 1.0 section 8.2 states, "After LPCPD# goes back inactive, the LPC I/F will always be reset

using LRST#”, this statement does not apply for mobile systems. LRST# (PCI_RESET#) will not occur if the LPC Bus

power was not removed. For example, when exiting a "light" sleep state (ACPI S1, APM POS), LRST# (PCI_RESET#)

will not occur. When exiting a "deeper" sleep state (ACPI S3-S5, APM STR, STD, soft-off), LRST# (PCI_RESET#) will

occur.

The LPCPD# pin is implemented as a “local” powergood for the LPC bus in the SIO1007. It is not used as a global pow-

ergood for the chip. It is used to reset the LPC block and hold it in reset.

An internal powergood is implemented in SIO1007 to minimize power dissipation in the entire chip.

Prior to going to a low-power state, the system will assert the LPCPD# signal. It will go active at least 30 microseconds

prior to the LCLK# (PCI_CLK) signal stopping low and power being shut to the other LPC I/F signals.

Upon recognizing LPCPD# active, the SIO1007 will drive the LDRQ# signal low or tri-state, and do so until LPCPD#

goes back inactive.

Upon recognizing LPCPD# inactive, the SIO1007 will drive its LDRQ# signal high.

See the Low Pin Count (LPC) Interface Specification Reference, Section 8.2.

SYNC Protocol

See the Low Pin Count (LPC) Interface Specification Reference, Section 4.2.1.8 for a table of valid SYNC values.

Typical Usage

The SYNC pattern is used to add wait states. For read cycles, the SIO1007 immediately drives the SYNC pattern upon

recognizing the cycle. The host immediately drives the sync pattern for write cycles. If the SIO1007 needs to assert wait

states, it does so by driving 0101 or 0110 on LAD[3:0] until it is ready, at which point it will drive 0000 or 1001. The

SIO1007 will choose to assert 0101 or 0110, but not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value.

The SYNC value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few

clocks. The SIO1007 uses a SYNC of 0101 for all wait states in a DMA transfer.

The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided for EPP cycles,

where the number of wait states could be quite large (>1 microsecond). However, the SIO1007 uses a SYNC of 0110

for all wait states in an I/O transfer.

The SYNC value is driven within 3 clocks.

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