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SIO1007 数据表(PDF) 83 Page - Microchip Technology |
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SIO1007 数据表(HTML) 83 Page - Microchip Technology |
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83 / 108 page  2005 - 2015 Microchip Technology Inc. DS00002020A-page 83 SIO1007 18.4.56 CR39 CR39 can only be accessed in the configuration state and after the CSR has been initialized to 39H. CR39 is GPIO Output Register and is used to select the output buffer of GP30-GP37pins. 18.4.57 CR3A CR3A can only be accessed in the configuration state and after the CSR has been initialized to 3AH. 5GP15 6GP16 7GP17 TABLE 18-50: CR39 GPIO Output Register 3 Type: R/W Default: 0XFF ON VTR POR BIT NO. BIT NAME DESCRIPTION 0 GP30 The bits in this register are used to select the output buffer type of the GP30-GP37 pins. 0=Push-pull 1=Open Drain 1GP31 2GP32 3GP33 4GP34 5GP35 6GP36 7GP37 TABLE 18-51: CR3A Logical Device Activate Register Type: R/W Default: 0x00 on VCC POR BIT NO. BIT NAME DESCRIPTION 0 SCE(FIR) 0 = Disables the host access to SCE (FIR) logical device (default). 1 = Enables the host access to SCE (FIR) logical device’s I/O runtime register space for the IRCC2.0 block. The I/O address is selected by the SCE(FIR) Base Address Registers. 1 Runtime Register 0 = Disables the host access to Runtime Register logical device (default). 1 = Enables the host access to Runtime Register logical device’s I/O register space for the Runtime Register block. The I/O address is selected by the Runtime Register Base Address Registers. 2 CIRCC2 0 = Disables the host access to CIRCC2 logical device (default). 1 = Enables the host access to CIRCC2 logical device’s I/O runtime register space for the CIRCC2 block. The I/O address is selected by the CIRCC2 Base Address Registers. TABLE 18-49: CR38 (CONTINUED) GPIO Pullup Register 1 Type: R/W Default: 0XFF ON VTR POR BIT NO. BIT NAME DESCRIPTION |
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