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SIO1007 数据表(PDF) 19 Page - Microchip Technology |
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SIO1007 数据表(HTML) 19 Page - Microchip Technology |
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19 / 108 page  2005 - 2015 Microchip Technology Inc. DS00002020A-page 19 SIO1007 APPLICATION NOTE: The system design must include weak pullup resistors in the docking station (~100KOhm) on the DLAD[3:0] and DLFRAME# signals to maintain an inactive docking LPC interface. 8.2 PortSwitch Docking Controls The SIO1007 provides three programmable bits which independently control the switching of the 14.318MHz clock and the dedicated docking PCICLK and the remainder of the LPC interface. The switching is provided in the Docking LPC Switch Register described in Section 8.3.1. 8.3 Registers 8.3.1 LOGICAL DEVICE FOR LPC DOCKING. The LPC Docking Base Address Registers (CR3B and CR3C) are used to select the base address of LPC Docking run- time register space. Valid addresses for LPC Docking runtime register space can be set to locations on single-byte boundaries from 100H - FFFH. To disable LPC Docking runtime register decoding, set the Docking Activate Register (CR3A)-bit 3 to ‘0’. When writing the LPC Docking Base Address registers (CR3B and CR3A) the set LPC Docking Acti- vate Register (CR3A) -bit 3 must be set to ‘0’. For detailed description of the LPC Docking Activate Register (CR3A) and the LPC Docking Base Address Registers (CR3B and CR3C.) See Section 18.0 for details description of Configuration Registers. 8.3.2 DOCKING LPC SWITCH REGISTER The Docking LPC Switch Register controls the connection and disconnection of the Docking LPC Interface. DLPC_SWITCH – D0 When DLPC SWITCH is asserted ‘1’, the bi-directional Docking LPC switches will be switched on and the DLPC pin connections will be connected to the LPC bus. When DLPC SWITCH is deasserted ‘0’, the DLPC pin connections will be disconnected from the LPC bus. TABLE 8-1: LPC DOCKING INTERFACE Host Side Interface Dock Side Interface Switch Control Bit LAD[3:0] DLAD[3:0] DLPC_SWITCH LFRAME# DLFRAME# DLPC_SWITCH LDRQ1# DLDRQ1# DLPC_SWITCH NCLKRUN NDCLKRUN DLPC_SWITCH SER_IRQ SER_IRQ DLPC_SWITCH LPC_CLK_33 DLPC_CLK_33 DCLK_33 SIO_14M DSIO_14M DCLK_14 TABLE 8-2: DOCKING LPC SWITCH REGISTER Address DLPC Runtime Registers Base Address + 0 Power VCC DEFAULT 00h D7 D6 D5 D4 D3 D2 D1 D0 TYPE R R RRR RR R/W BIT Name RESERVED DCLK_1 4 DCLK_3 3 DLPCSWITCH |
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