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SIO1007 数据表(PDF) 9 Page - Microchip Technology

部件名 SIO1007
功能描述  LPC Super I/O LPC IrDA Hot Docking Chip with UART
PDF  108 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

SIO1007 数据表(HTML) 9 Page - Microchip Technology

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 2005 - 2015 Microchip Technology Inc.
DS00002020A-page 9
SIO1007
55
nRTS1
(SYSOPT0)
Active low Request to Send outputs for
the Serial Port. Handshake output
signal notifies modem that the UART is
ready to transmit data. This signal can
be programmed by writing to bit 1 of
the Modem Control Register (MCR).
The hardware reset will reset the nRTS
signal to inactive mode (high). nRTS is
forced inactive during loop mode
operation.
At the deasserting edge of PCIRST#,
the nRTS pin is latched to determine
the configuration base address: 0 =
Index Base I/O Address bits A[7:0]= 2E
Hex; 1 = Index Base I/O Address bits
A[7:0]==4E Hex.
O8
N/A
VCC
4-2
53
TXD1
Transmit serial data output for port 1.
O12
N/A
VCC
56
nCTS1
Active low Clear to Send inputs for the
serial port. Handshake signal which
notifies the UART that the modem is
ready to receive data. The CPU can
monitor the status of nCTS signal by
reading bit 4 of Modem Status Register
(MSR). A nCTS signal state change
from low to high after the last MSR read
will set MSR bit 0 to a 1. If bit 3 of the
Interrupt Enable Register is set, the
interrupt is generated when nCTS
changes state. The nCTS signal has no
effect on the transmitter.
Note:
Bit 4 of MSR is the
complement of nCTS.
I
VCC
N/A
57
nDTR1
(SYSOPT1)
Active low Data Terminal Ready
outputs for the serial port. Handshake
output signal notifies modem that the
UART is ready to establish data
communication link. This signal can be
programmed by writing to bit 0 of
Modem Control Register (MCR). The
hardware reset will reset the nDTR
signal to inactive mode (high). nDTR is
forced inactive during loop mode
operation.
At the deasertting edge of PCIRST#,
the nDTR1 pin is latched to determine
the configuration base address: 0 =
Index Base I/O Address bits A[15:8]=00
Hex; 1 = Index Base I/O Address bits
A[15:8]= 16 Hex.
OP14
N/A
VCC
4-2
TABLE 4-1:
PIN FUNCTIONS (CONTINUED)
STQFP
Pin #
Name
Description
Buffer
Name
Input
Buffer
Power
Well
Output
Buffer
Power
Well
Notes



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