SIO1007 datasheet(68/108 Pages) MICROCHIP

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SIO1007

DS00002020A-page 68

 2005 - 2015 Microchip Technology Inc.

18.4.21

CR15

CR15 can only be accessed in the configuration state and after the CSR has been initialized to 15H. CR15 shadows the

bits in the write-only UART1 run-time FCR register.

18.4.22

CR16

CR16 can only be accessed in the configuration state and after the CSR has been initialized to 16H. CR16 shadows the

bits in the write-only UART2 run-time FCR register. See CR15 for register description.

18.4.23

CR17

18.4.24

CR18

CR18 can only be accessed in the configuration state and after the CSR has been initialized to 18h. CR18 is used to

select the IRQ channel for CIRCC2 and the DMA channel for the CIRCC2 port. Any unselected IRQ output is in tristate.

Shared IRQs are not supported in the SIO1007.

TABLE 18-17: CR15

UART1 FCR Shadow Register

Type: R

Default: N/A

BIT NO.

BIT NAME

DESCRIPTION

FIFO Enable

Setting this bit to a logic "1" enables both the XMIT and RCVR FIFOs

RCVR FIFO Reset

Setting this bit to a logic "1" clears all bytes in the RCVR FIFO and resets

its counter logic to 0. This bit is self clearing.

XMIT FIFO Reset

Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets

its counter logic to 0. This bit is self-clearing.

DMA Mode Select

Writing to this bit has no effect on the operation of the UART.

4,5

Reserved

Read Only. A read returns 0.

6,7

RCVR Trigger

These bits are used to set the trigger level for the RCVR FIFO interrupt.

BIT7

BIT6

RCVR FIFO TRIGGER LEVEL (BYTES)

001

014

108

1114

TABLE 18-18: CR18

CIRCC2 Interrupt/DMA Selection

Type: R/W

Default: 0x00 on VCC POR

BIT NO.

BIT NAME

DESCRIPTION

3:0

CIRCC2 DMA

Select

These bits are used to select DMA for CIRCC2 port. See DMA encoding

for CR18 (see Table 18-20).

7:4

CIRCC2 IRQ Select These bits are used to select IRQ for CIRCC2 port. See IRQ encoding for

CR18 (see Table 18-19).

Note:

A CIRCC2 IRQ event will only be generated if an SCE event is

active and enabled and the CIRCC2 Base I/O Address is in the

active range (i.e., greater than 100h)

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