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SIO1007 数据表(PDF) 90 Page - Microchip Technology |
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SIO1007 数据表(HTML) 90 Page - Microchip Technology |
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90 / 108 page ![]() SIO1007 DS00002020A-page 90 2005 - 2015 Microchip Technology Inc. 20.0 TIMING DIAGRAMS For the Timing Diagrams shown, the following capacitive loads are used on outputs. Note 20-1 Internal write-protection period after Vcc passes 2.7 volts on power-up. Name Capacitance Total (pF) SER_IRQ 50 nLAD[3:0] 50 nLDRQ 50 TXD1 50 nCLKRUN 50 FIGURE 20-1: POWER-UP TIMING Name Description MIN TYP MAX Units t1 Vcc Slew from 2.7V to 0V 300 s t2 Vcc Slew from 0V to 2.7V 100 s t3 All Host Accesses After Powerup (Note 20-1)125 500 s FIGURE 20-2: INPUT CLOCK TIMING Name Description MIN TYP MAX Units t1 Clock Cycle Time for 14.318MHZ 69.84 ns t2 Clock High Time/Low Time for 14.318MHz 20 35 ns Clock Rise Time/Fall Time (not shown) 5 ns t3 Vc c Al l H o s t A cce s s e s t2 t1 |
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