SIO1007 datasheet(17/108 Pages) MICROCHIP

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DS00002020A-page 17

SIO1007

SYNC Timeout

The SYNC value is driven within 3 clocks. If the host observes 3 consecutive clocks without a valid SYNC pattern, it will

abort the cycle.

The SIO1007 does not assume any particular timeout. When the host is driving SYNC, it may have to insert a very large

number of wait states, depending on PCI latencies and retries.

SYNC Patterns and Maximum Number of SYNCS

If the SYNC pattern is 0101, then the host assumes that the maximum number of SYNCs is 8.

If the SYNC pattern is 0110, then no maximum number of SYNCs is assumed. The SIO1007 has protection mechanisms

to complete the cycle.

SYNC Error Indication

The SIO1007 reports errors via the LAD[3:0] = 1010 SYNC encoding.

If the host was reading data from the SIO1007, data will still be transferred in the next two nibbles. This data may be

invalid, but it will be transferred by the SIO1007. If the host was writing data to the SIO1007, the data had already been

transferred.

In the case of multiple byte cycles, such as DMA cycles, an error SYNC terminates the cycle. Therefore, if the host is

transferring 4 bytes from a device, if the device returns the error SYNC in the first byte, the other three bytes will not be

transferred.

I/O and DMA START Fields

I/O and DMA cycles use a START field of 0000.

Reset Policy

The following rules govern the reset policy:

When PCI_RESET# goes inactive (high), the clock is assumed to have been running for 100usec prior to the

removal of the reset signal, so that everything is stable. This is the same reset active time after clock is stable

that is used for the PCI bus.

When PCI_RESET# goes active (low):

the host drives the LFRAME# signal high, tristates the LAD[3:0] signals, and ignores the LDRQ# signal.

the SIO1007 ignores LFRAME#, tristate the LAD[3:0] pins and drive the LDRQ# signal inactive (high).

7.1.2

LPC TRANSFERS

Wait State Requirements

I/O Transfers

The SIO1007 inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used

for all I/O transfers. The exception to this is for transfers where IOCHRDY would be deasserted in an ISA transfer (i.e.,

IrCC transfers) in which case the sync pattern of 0110 is used and a large number of syncs may be inserted (up to 330

which corresponds to a timeout of 10us).

DMA Transfers

The SIO1007 inserts three wait states for a DMA read and four wait states for a DMA write cycle. A SYNC of 0101 is

used for all DMA transfers.

See the example timing for the LPC cycles in the Timing Diagrams section.

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