SIO1007 datasheet(15/108 Pages) MICROCHIP

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DS00002020A-page 15

SIO1007

7.0

LPC INTERFACE

The following sub-sections specify the implementation of the LPC bus.

7.1

LPC Interface Signal Definition

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz elec-

trical signal characteristics.

LPC Cycles

The following cycle types are supported by the LPC protocol.

The SIO1007 ignores cycles that it does not support.

Field Definitions

The data transfers are based on specific fields that are used in various combinations, depending on the cycle type.

These fields are driven onto the LAD[3:0] signal lines to communicate address, control and data information over the

LPC bus between the host and the SIO1007. See the Low Pin Count (LPC) Interface Specification Revision 1.0 from

Intel, Section 4.2 for definition of these fields.

LFRAME# Usage

LFRAME# is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out

condition. This signal is to be used by the SIO1007 to know when to monitor the bus for a cycle.

This signal is used as a general notification that the LAD[3:0] lines contain information relative to the start or stop of a

cycle, and that the SIO1007 monitors the bus to determine whether the cycle is intended for it. The use of LFRAME#

allows the SIO1007 to enter a lower power state internally. There is no need for the SIO1007 to monitor the bus when

it is inactive, so it can decouple its state machines from the bus, and internally gate its clocks.

When the SIO1007 samples LFRAME# active, it immediately stops driving the LAD[3:0] signal lines on the next clock

and monitor the bus for new cycle information.

The LFRAME# signal functions as described in the Low Pin Count (LPC) Interface Specification Revision 1.0.

I/O Read and Write Cycles

The SIO1007 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will gen-

erally have minimal Sync times. The minimum number of wait-states between bytes is 1.

Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will break it up

into 8-bit transfers.

Signal Name

Type

Description

LAD[3:0]

I/O

LPC address/data bus. Multiplexed command, address and data bus.

LFRAME#

Input

Frame signal. Indicates start of new cycle and termination of broken cycle

PCI_RESET#

Input

PCI Reset. Used as LPC Interface Reset.

LDRQ#

Output

Encoded DMA/Bus Master request for the LPC interface.

IO_PME#

Power Mgt Event signal. Allows the SIO1007 to request wakeup.

LPCPD#

Input

Powerdown Signal. Indicates that the SIO1007 should prepare for power to be shut on

the LPC interface.

SER_IRQ

I/O

Serial IRQ.

PCI_CLK

Input

PCI Clock.

CLKRUN#

I/OD

Clock Run. Allows the SIO1007 to request the stopped PCI_CLK be started.

Cycle Type

Transfer Size

I/O Write

1 Byte

I/O Read

1 Byte

DMA Write

1 Byte

DMA Read

1 Byte

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