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SIO1007 数据表(PDF) 60 Page - Microchip Technology |
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SIO1007 数据表(HTML) 60 Page - Microchip Technology |
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60 / 108 page ![]() SIO1007 DS00002020A-page 60 2005 - 2015 Microchip Technology Inc. Note 18-3 The bits that control the direction, polarity and output buffer type of each GPIO also affect the alternate function on the GPIO. 18.4 Configuration Register Detailed Description 18.4.1 CR00 CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. CR27 R - 0x00 - Reserved CR28 R/W - 0x00 - UART IRQ Select CR29 R/W - 0x80 - IRQIN1/HPMODE/SIRQ_CLKRUN_En CR2A R/W - 0x00 - IRQIN2 CR2B R/W - 0x00 - SCE (FIR) Base Address - Low Byte CR2C R/W - 0x0F - SCE (FIR) DMA Select CR2D R/W - 0x03 - IR Half Duplex Timeout CR2E R/W - 0x00 - Software Select A CR2F R/W - 0x00 - Software Select B CR30 R/W - 0x00 - Runtime Register Base Address - Low Byte CR31 R/W - - 0x00 GPIO Direction Register 1 CR32 R/W - - 0x00 GPIO Polarity Register 1 CR33 R/W - 0xFF- GPIO Output Type Register 1 CR34 R/W - - 0x01 Alternate Function Register CR35 R/W - - 0x00 GPIO Direction Register 3 CR36 R/W - - 0x00 GPIO Polarity Register 3 CR37 R/W - - 0xFF GPIO PULLUP Register 3 CR38 R/W - - 0xFF GPIO PULLUP Register 1 CR39 R/W - - 0xFF GPIO Output Type Register 3 CR3A R/W 0x00 Logical Device Activate Register CR3B R/W 0x00 LPC Docking Base Address Register High Byte CR3C R/W 0x00 LPC Docking Base Address Register Low Byte TABLE 18-4: CR00 Valid Configuration Cycle Type: R/W Default: 0X00 ON VCC POR BIT NO. BIT NAME DESCRIPTION 6:0 Reserved Read Only. A read returns 0 7Valid A high level on this software-controlled bit can be used to indicate that a valid configuration cycle has occurred. The control software must take care to set this bit at the appropriate times. Set to zero after power up. This bit has no effect on any other hardware in the chip. TABLE 18-3: CONFIGURATION REGISTERS SUMMARY (CONTINUED) Register Index Type PCI Reset (Note 18-3) VCC POR VTR POR Register |
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