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SIO1007 数据表(PDF) 38 Page - Microchip Technology |
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SIO1007 数据表(HTML) 38 Page - Microchip Technology |
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38 / 108 page  SIO1007 DS00002020A-page 38 2005 - 2015 Microchip Technology Inc. 10.4.2 CIRCC2 OPERATIONAL POWER STATES The CIRCC2 block is powered by VTR. This block is fully operational under VCC and supports NEC PPM and RC5 wake events under VTR only (VCC=0V). When VCC is on, the CIRCC2 clock source is derived from the 14.318MHz clock input. When VCC is off, the CIRCC2 clock source may be derived from the internal PLL to provide clock support for the CIR wake features. The CIR wake features are only operational if the CLOCKI32 pin is connected to a 32kHz suspend clock, the alternate function on the GP13/IRQIN1/CLKI32 pin is configured for CLOCKI32, and the CLOCKI32 PLL is powered. The CLOCKI32 signal is the alternate function on the GP13/IRQIN1/CLKI32 pin. The functions for this pin are selected by the CR34 on page 80. The CLOCKI32 PLL is enabled when VCC transitions to the OFF state if the PLL is Powered. The PLL defaults to the off state to conserve power. To enable the PLL to operate when the device is in a sleep state (VTR Only) the CIRCC2 PLL can be enabled via the CIRCC2 PLL Power bit located in bit[5] of CR02. See CR02 on page 61. 10.4.3 CONFIGURING THE CIRCC2 BLOCK The CIRCC2 block defaults to the powered down state. To enable the CIRCC2 block to be operational the CIRCC2 log- ical Device Base address must initialized via CR1F and CR20, the activate bit in CR3A-bit2 set to one and the CIRCC2 Power Down bit in CR02 must be set to one. The configuration and control registers for the CIRCC2 block are located in the SCE registers defined in the Consumer Infrared Communications Controller 2 (CIRCC2) specification. Some of these registers are shadowed in the SIO1007 Configuration Registers. The following table summarizes all the registers that are shadowed in the configuration register space for the CIRCC2 block. The table lists the Configuration register location, the corresponding SCE register location, the read/write ability in both locations and the POR conditions for each corresponding location. Note 10-2 The CIRCC2 Half Duplex Timeout register (shaded in the table below) is reset on a VCC POR in Config space, which overrides the SCE condition to reset on VTR POR only Note 10-3 The CIRCC2 SCE registers are implemented as blocks of registers that are directly addressable at the programmed CIRCC2 Base I/O Address plus an offset. TABLE 10-3: SUMMARY OF POR AND READ/WRITE CONDITIONS FOR CIRCC2 SHADOWED REGISTERS/BITS CR# Configuration Register/Bits SCE/ACE Registers/Bits Read/Write POR Condition for Specific Bits CR SCE CR SCE CR0A ECP FIFO Threshold/IR MUX • Bits[5:4] CIRCC2 Output Mux SCE: Register Block 1, Address 1, • Bits[D7:D6] Output Mux for CIRCC2 Block R/W R/W VTR Only VTR Only CR0B CIRCC2 Mode Register • Bits[5:0] SCE: Register Block 1, Address 0, • Bits[5:0] are shadowed in Register Block 1, Address 0, bits[D5:D0] R/W R/W VTR Only VTR Only CR18 CIRCC2 IRQ/DMA Select Register • Bits[7:4] CIRCC2 IRQ Select • Bits[3:0] CIRCC2 DMA Select SCE: Register Block 3, Address 4, • Bits[7:4] CIRCC2 IRQ Select • Bits[3:0] CIRCC2 DMA Select R/W Read- Only VCC - CR19 CIRCC2 Software Select A SCE: Register Block 3, Address 5 R/W Read- Only VCC - CR1A CIRCC2 Software Select B SCE: Register Block 3, Address 6 R/W Read- Only VCC - CR1B CIRCC2 Half Duplex Timeout (Note 10-2) SCE: Register Block 5, Address 1 Yes Yes VCC VTR Only |
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