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SIO1007 数据表(PDF) 47 Page - Microchip Technology |
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SIO1007 数据表(HTML) 47 Page - Microchip Technology |
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47 / 108 page  2005 - 2015 Microchip Technology Inc. DS00002020A-page 47 SIO1007 14.0 GENERAL PURPOSE I/O The SIO1007 provides a set of flexible Input/Output control functions to the system designer through the 16 inde- pendently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled to generate an SMI and a PME. 14.1 GPIO Pins The following pins include GPIO functionality as defined in the table below. Note 14-1 These pins have input buffers into the wakeup logic that are powered by VTR. 14.2 Description Each GPIO port has a 1-bit data register. GPIOs are controlled by GPIO control registers located in the Configuration section. The data register for each GPIO port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 and GP3. The bits in these registers reflect the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an output: The value written to the bit goes to the GPIO pin. The value is latched on reads and writes. Although the bits in GP1 and GP3 default to 0x00 at VTR POR, the value read is affected by the GPIO pin state. Each GPIO pin’s state at VCC POR is controlled by the pin’s programmed configuration and the external interface (e.g. input driven low by external device.) Each GPIO pin has programmable configuration bits in CR31-CR39 which control direc- tion, output types, polarity, and internal pull-ups. For example, the GPIO internal pull-ups are controlled by CR37 and CR38 and default at VTR POR to pull-up enabled (logic ‘1’.) If not reprogrammed any open input will have logic ‘1’ at VCC POR. This will affect the corresponding bit in the GP1 and GP3 runtime register. The GPIO data registers are located in the Runtime Register block; see the Runtime Registers section. The GPIO ports with their alternate functions and configuration state register addresses are listed in Table 14-2. TABLE 14-1: GPIO PIN FUNCTIONALITY Name Power Well Default On VTR POR PME/SMI Function GP10 VCC (Note 14-1) Input PME/SMI GP11 VCC (Note 14-1) Input PME/SMI GP12/IO_SMI# VCC (Note 14-1) Input IO_SMI#/ PME/SMI GP13/IRQIN1/CLKI32 VCC (Note 14-1) Input PME/SMI GP14/IRQIN2 VCC (Note 14-1) Input PME/SMI GP15 / CIRRX VCC (Note 14-1) Input PME/SMI GP16 / CIRTX VCC (Note 14-1) Input PME/SMI GP17 VCC (Note 14-1) Input PME/SMI GP30 VCC (Note 14-1) Input PME GP31 VCC (Note 14-1) Input PME GP32 VCC (Note 14-1) Input PME GP33 VCC (Note 14-1) Input PME GP34 VCC (Note 14-1) Input PME GP35 VCC (Note 14-1) Input PME GP36 VCC (Note 14-1) Input PME GP37 VCC (Note 14-1) Input PME |
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