SIO1007 datasheet(54/108 Pages) MICROCHIP

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SIO1007

DS00002020A-page 54

 2005 - 2015 Microchip Technology Inc.

PME_STS1

Default = 0x00

on VTR POR

See Note 17-2

(R/W)

PME Wake Status Register 1

This register indicates the state of the individual PME wake sources,

independent of the individual source enables or the PME_En bit.

If the wake source has asserted a wake event, the associated PME Wake

Status bit will be a “1”.

Bit[0] GP10

Bit[1] GP11

Bit[2] GP12

Bit[3] GP13

Bit[4] GP14

Bit[5] GP15

Bit[6] GP16

Bit[7] GP17

The PME Wake Status register is not affected by Vcc POR, SOFT RESET

or PCI RESET.

Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake

Status Register has no effect.

PME_STS2

Default = 0x00

on VTR POR

(R/W)

PME Wake Status Register 2

This register indicates the state of the individual PME wake sources,

independent of the individual source enables or the PME_En bit.

If the wake source has asserted a wake event, the associated PME Wake

Status bit will be a “1”.

Bit[0] RI1

Bit[1] IRRX2

Bit[2] CIRCC2

Bit[7:3] Reserved

The PME Wake Status register is not affected by Vcc POR, SOFT RESET

or PCI RESET.

Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake

Status Register has no effect.

PME_STS3

Default = 0x00

on VTR POR

See Note 17-2

(R/W)

PME Wake Status Register 3

This register indicates the state of the individual PME wake sources,

independent of the individual source enables or the PME_EN bit.

If the wake source has asserted a wake event, the associated PME Wake

Status bit will be a “1”.

Bit[0] GP30

Bit[1] GP31

Bit[2] GP32

Bit[3] GP33

Bit[4] GP34

Bit[5] GP35

Bit[6] GP36

Bit[7] GP37

The PME Wake Status register is not affected by Vcc POR, SOFT RESET

or PCI RESET.

Writing a “1” to Bit[7:0] will clear it. Writing a “0” to any bit in PME Wake

Status Register has no effect.

PME_EN1

Default = 0x00

on VTR POR

(R/W)

PME Wake Enable Register 1

This register is used to enable individual SIO1007 PME wake sources onto

the IO_PME# wake bus.

When the PME Wake Enable register bit for a wake source is active (“1”), if

the source asserts a wake event so that the associated status bit is “1” and

the PME_En bit is “1”, the source will assert the IO_PME# signal.

When the PME Wake Enable register bit for a wake source is inactive (“0”),

the PME Wake Status register will indicate the state of the wake source but

will not assert the IO_PME# signal.

Bit[0] GP10

Bit[1] GP11

Bit[2] GP12

Bit[3] GP13

Bit[4] GP14

Bit[5] GP15

Bit[6] GP16

Bit[7] GP17

The PME Wake Enable register is not affected by Vcc POR, SOFT RESET

or PCI RESET.

TABLE 17-2:

RUNTIME REGISTERS BLOCK DESCRIPTION (CONTINUED)

Name/Default

Offset

Description

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