SIO1007 datasheet(43/108 Pages) MICROCHIP

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DS00002020A-page 43

SIO1007

The SER_IRQ data frame supports IRQ2 from a logical device on Period 3, which can be used for the System Manage-

ment Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register.

Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2.

SER_IRQ Period 14 is used to transfer IRQ13. Logical devices Serial Port 1, Serial Port 2 have IRQ13 as a choice for

their primary interrupt.

The SMI is enabled onto the SMI frame of the Serial IRQ via bit 6 of SMI Enable Register 2 and onto the nIO_SMI pin

via bit 7 of the SMI Enable Register 2.

12.1.3

STOP CYCLE CONTROL

Once all IRQ/Data Frames have completed the Host Controller will terminate SER_IRQ activity by initiating a Stop

Frame. Only the Host Controller can initiate the Stop Frame. A Stop Frame is indicated when the SER_IRQ is low for

two or three clocks. If the Stop Frame’s low time is two clocks then the next SER_IRQ Cycle’s sampled mode is the

Quiet mode; and any SER_IRQ device may initiate a Start Frame in the second clock or more after the rising edge of

the Stop Frame’s pulse. If the Stop Frame’s low time is three clocks then the next SER_IRQ Cycle’s sampled mode is

the Continuous mode; and only the Host Controller may initiate a Start Frame in the second clock or more after the rising

edge of the Stop Frame’s pulse.

12.1.4

LATENCY

Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported

IRQ/Data Frames of seventeen, will range up to 96 clocks (3.84

S with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI

Bus). If one or more PCI to PCI Bridge is added to a system, the latency for IRQ/Data updates from the secondary or

tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses.

12.1.5

EOI/ISR READ LATENCY

Any serialized IRQ scheme has a potential implementation issue related to IRQ latency. IRQ latency could cause an

EOI or ISR Read to precede an IRQ transition that it should have followed. This could cause a system fault. The host

interrupt controller is responsible for ensuring that these latency issues are mitigated. The recommended solution is to

delay EOIs and ISR Reads to the interrupt controller by the same amount as the SER_IRQ Cycle latency in order to

ensure that these events do not occur out of order.

12.1.6

AC/DC SPECIFICATION ISSUE

All SER_IRQ agents must drive / sample SER_IRQ synchronously related to the rising edge of PCI bus clock. The

SER_IRQ pin uses the electrical specification of PCI bus. Electrical parameters will follow PCI spec. section 4, sustained

tri-state.

12.1.7

RESET AND INITIALIZATION

The SER_IRQ bus uses PCI_RESET# as its reset signal. The SER_IRQ pin is tri-stated by all agents while PCI_RE-

SET# is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible

for starting the initial SER_IRQ Cycle to collect system’s IRQ/Data default values. The system then follows with the Con-

tinuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SER_IRQ Cycles. It is Host Controller’s respon-

sibility to provide the default values to 8259’s and other system logic before the first SER_IRQ Cycle is performed. For

SER_IRQ system suspend, insertion, or removal application, the Host controller should be programmed into Continuous

(IDLE) mode first. This is to ensure SER_IRQ bus is in IDLE state before the system configuration changes.

12.2

Routable IRQ Inputs

The routable IRQ input (IRQINx) functions are muxed onto GP13 and GP14 respectively as inputs. The IRQINx pin’s

IRQ time slot in the Serial IRQ stream is selected via a 4-bit control register for each IRQIN function (CR29 for IRQIN1,

CR2A for IRQIN2). A value of 0000 disables the IRQ function.

The part is able to generate a PME and an SMI from both of the IRQ inputs through the GPIO bits in the PME and SMI

status and enable registers. The edge is programmable through the polarity bit of the GPIO control register.

User Note: In order to use an IRQ for one of the IRQINx inputs that are muxed on the GPIO pins, the corresponding

IRQ must not be used for any of the devices in the SIO1007. Otherwise contention may occur.

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