SIO1007 datasheet(52/108 Pages) MICROCHIP

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SIO1007

DS00002020A-page 52

 2005 - 2015 Microchip Technology Inc.

16.0

PME SUPPORT

The SIO1007 offers support for Power Management Events (PMEs), also referred to as System Control Interrupt (SCI)

events in an ACPI system. A power management event is indicated to the chipset via the assertion of the IO_PME#

signal. In the SIO1007, the IO_PME# is asserted by active transitions on the ring indicator inputs nRI1 and nRI2, and

programmable edges on GPIO pins. The nIO_PME pin can be programmed to be active high or active low via bit 5 in

the GPIO Polarity Register 2 (CR34). The nIO_PME pin function defaults to active low, open-drain output. The output

buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 in the GPIO Output Type Register

(CR39). This pin is powered by VTR. See the Configuration section for description on these registers.

PME functionality is controlled by the PME status and enable registers in the runtime registers block, which is located

at the address programmed in register 0x30 in the Configuration section. The PME Enable bit, PME_EN, globally con-

trols PME Wake-up events. When PME_EN is inactive, the IO_PME# signal can not be asserted. When PME_EN is

asserted, any wake source whose individual PME Wake Enable register bit is asserted can cause IO_PME# to become

asserted.

The PME Status register indicates that an enabled wake source has occurred and if the PME_EN bit is set, asserted

the IO_PME# signal. The PME Status bit is asserted by active transitions of PME wake sources. PME_STS will become

asserted independent of the state of the global PME enable, PME_EN.

The following pertains to the PME status bits for each event:

• The output of the status bit for each event is combined with the corresponding enable bit to set the PME status bit.

• The status bit for any pending events must be cleared in order to clear the PME_STS bit. Status bits are cleared

on a write of ‘1’.

For the GPIO events, the polarity of the edge used to set the status bit and generate a PME is controlled by the GPIO

Polarity Registers in the Configuration section. For non-inverted polarity (default) the status bit is set on the low-to-high

edge. Status bits are cleared on a write of ‘1’.

In the SIO1007 the IO_PME# pin can be programmed to be an open drain, active low, driver. The SIO1007 IO_PME#

pin is fully isolated from other external devices that might pull the IO_PME# signal low; i.e., the IO_PME# signal is capa-

ble of being driven high externally by another active device or pullup even when the SIO1007 VCC is grounded, provid-

ing VTR power is active.

16.1

PME Registers

The PME registers are run-time registers as follows. These registers are located in system I/O space at an offset from

Runtime Registers Block, the address programmed at register 0x30 in the Configuration section.

The following registers are for GPIO PME events:

• PME Wake Status 1 (PME_STS1), PME Wake Enable 1 (PME_EN1)

• PME Wake Status 2 (PME_STS2), PME Wake Enable 2 (PME_EN2)

• PME Wake Status 3 (PME_STS3), PME Wake Enable 3 (PME_EN3)

See PME register description in the Runtime Registers Section.

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