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SIO1007 数据表(PDF) 100 Page - Microchip Technology

部件名 SIO1007
功能描述  LPC Super I/O LPC IrDA Hot Docking Chip with UART
PDF  108 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

SIO1007 数据表(HTML) 100 Page - Microchip Technology

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SIO1007
DS00002020A-page 100
 2005 - 2015 Microchip Technology Inc.
21.0
XNOR-CHAIN TEST MODE
The SIO1007 provides board test capability through the implementation of XNOR chain. See following sub-sections.
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard during assembly
and test operations. See Figure 21-1 below. When the chip is in the XNOR chain test mode, setting the state of any of
the input pins to the opposite of its current state will cause the output of the chain to toggle.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is activated, the
SIO1007 pin functions are disconnected from the device pins, which all become input pins except for one output pin at
the end of XNOR-Chain.
The tests that are performed when the XNOR-Chain test structure is activated require the board-level test hardware to
control the device pins and observe the results at the XNOR-Chain output pin.
21.1
Entering and Exiting Test Mode
XNOR-Chain test mode can be entered as follows:
On the rising (deasserting) edge of nPCI_RESET, drive nLFRAME low and drive LAD[0] low.
Exit XNOR-Chain test mode as follows:
On the rising (deasserting) edge of nPCI_RESET, drive either nLFRAME or LAD[0] high.
The nPCI_RESET pin is not included in the XNOR-Chain. The XNOR-Chain output is on the nIO_PME pin. See the
following subsections for more details.
21.2
Pin List of XNOR Chain
All pins on the chip are inputs to the first XNOR chain, with the exception of the following:
1.
VCC (5 pins) and VTR (1 pin).
2.
VSS (6 pins).
3.
nPCI_RESET
4.
nIO_PME This is the chain output.
To put the chip in the first XNOR chain test mode, tie LAD0 and nLFRAME low. Then toggle nPCI_RESET from a low
to a high state. Once the chip is put into XNOR chain test mode, LAD0 and nLFRAME become part of the chain.
To exit the first XNOR chain test mode tie LAD0 or nLFRAME high. Then toggle nPCI_RESET from a low to a high state.
A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test mode has been exited, observe
the output at nIO_PME. Toggling any of the input pins in the chain should not cause its state to change.
FIGURE 21-1:
XNOR-CHAIN TEST STRUCTURE
I/O#1
I/O#2
I/O#3
I/O#n
XNor
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