SIO1007 datasheet(12/108 Pages) MICROCHIP

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SIO1007

DS00002020A-page 12

 2005 - 2015 Microchip Technology Inc.

5.0

POWER FUNCTIONALITY

The SIO1007 has two power planes: VCC and VTR. The SIO1007 is a 3.3 Volt part. Both the VCC and VTR supply are

3.3 Volts (nominal). See the Operational Description Section and the Maximum Current Values subsection.

5.1

3.3 Volt Operation / 5 Volt Tolerance

The SIO1007 is a 3.3 Volt part. It is intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant and ChiPro-

tect.

A 5V tolerant pin input voltage is 5.5V max, and the I/O buffer output pads are backdrive protected.

ChiProtect

pins can be connected to a powered up external input or output device when the SIO1007 is unpowered. For

example, this includes an external device outputting a high to an unpowered pin if the voltage does not exceed the Max-

imum Ratings, Positive Voltage on any pin, with respect to Ground parameter (+5.5V).

See Table 4-1 and the associated Note 4-4 to identify the non-5V tolerant pins.

5.2

VTR Support

The SIO1007 requires a trickle supply (VTR) to provide sleep current for the programmable wake-up events in the PME

interface when VCC is removed. If the SIO1007 is not intended to provide wake-up capabilities on standby current, VTR

can be connected to VCC. The VTR pin generates a VTR Power-on-Reset signal to initialize these components.

5.3

Internal PWRGOOD

An internal PWRGOOD logical control is included to minimize the effects of pin-state uncertainty in the host interface as

VCC cycles on and off. When the internal PWRGOOD signal is “1” (active), VCC > 2.3V (nominal), and the SIO1007 host

interface is active. When the internal PWRGOOD signal is “0” (inactive), VCC  2.3V (nominal), and the SIO1007 host

interface is inactive; that is, LPC bus reads and writes will not be decoded.

The SIO1007 device pins IO_PME#, nRI1, IRRX2, IRTX2, IRMODE/IRRX3 and all GPIOs (as input) are part of the PME

interface and remain active when the internal PWRGOOD signal has gone inactive, provided VTR is powered. See

Trickle Power Functionality section.

5.4

Trickle Power Functionality

When the SIO1007 is running under VTR only, the PME wakeup events are active and (if enabled) able to assert the

IO_PME# pin active low. The following lists the wakeup events:

• UART 1 Ring Indicator

• IR Receive (IRRX2)

• CIRCC2 block

• GPIOs for wakeup. See below.

The following requirements apply to all I/O pins that are specified to be 5 volt tolerant.

• I/O buffers that are wake-up event compatible are powered by VCC. Under VTR power (VCC=0), these pins may

only be configured as inputs. These pins have input buffers into the wakeup logic that are powered by VTR.

• I/O buffers that may be configured as either push-pull or open drain under VTR power (VCC=0), are powered by

VTR. This means they will, at a minimum, source their specified current from VTR even when VCC is present.

Note:

If VTR is to be used for programmable wake-up events when VCC is removed, VTR must be at its full mini-

mum potential at least 10

s before V

CC begins a power-on cycle. When VTR and VCC are fully powered,

the potential difference between the two supplies must not exceed 500mV.

Note:

The GP13/IRQIN1/CLKI32 pin must be connected to a 32kHz suspend clock source (i.e., available under

VTR and the CLKI32 alternate function programmed on the GP13/IRQIN1/CLKI32 pin) for the NEC PPM

and RC5 wake events to be operational.

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