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SIO1007 数据表(PDF) 61 Page - Microchip Technology |
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SIO1007 数据表(HTML) 61 Page - Microchip Technology |
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61 / 108 page ![]() 2005 - 2015 Microchip Technology Inc. DS00002020A-page 61 SIO1007 18.4.2 CR01 CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. 18.4.3 CR02 CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. Note 18-4 Power Control bits disable the respective logical device and associated pins, however the power control bit does not disable the selected address range for the logical device. To disable the host address registers software must clear the activate bits in CR3A, the Logical Device Activate Register. Devices that are powered down and still activated will participate in Plug-and-Play range checking. 18.4.4 CR03 Register CR03 is reserved. The default value of this register after power up is 00H. TABLE 18-5: CR01 CR Lock Type: R/W Default: 0X80 ON VCC POR; BIT[7] = 1 ON PCI RESET BIT NO. BIT NAME DESCRIPTION 6:0 Reserved Read Only. A read returns “0”. 7 Lock CRx A high level on this bit enables the reading and writing of CR00 –CR39 (Default). A low level on this bit disables the reading and writing of CR00 – CR39. Note: Once the Lock CRx bit is set to “0”, this bit can only be set to “1” by a PCI reset or power-up reset. TABLE 18-6: CR02 UART and IR Power Type: R/W Default: 0x20 on VTR POR; 0xx00000VCC POR; Bit[7] = 0 on PCI Reset BIT NO. BIT NAME DESCRIPTION 0-2 Reserved Read Only. A read returns “0”. 3 UART1 Power Control Note 18-4 0= Primary Serial Port are in Power Down Mode. (default) 1= Enables normal operation of the Primary Serial Port 4 Reserved Read Only. A read returns “0”. 5 CIRCC2 PLL Power Down CIRCC PLL Power (Note: This bit is reset on VTR POR only) = 0 The 32.768kHz clock PLL is running and can replace the 14.318MHz clock source for the CIRCC2 Wake Event. PLL selected by internal PWRGOOD signal. = 1 The 32.768kHz clock PLL is unpowered (default) 6 CIRCC2 Power Control Note 18-4 0= SCE/FIR block is in Power Down Mode. (default) 1= Enables normal operation of the SCE/CIR block Note: This bit is reset on VTR POR only. 7 UART2 Power Control Note 18-4 0= Secondary Serial Port including the SCE/FIR block are in Power Down Mode. (default on VCC POR and PCI Reset) 1=Enables normal operation of the Secondary Serial Port, including the SCE/FIR block. |
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