SIO1007 datasheet(70/108 Pages) MICROCHIP

70 / 108 page

SIO1007

DS00002020A-page 70

 2005 - 2015 Microchip Technology Inc.

18.4.26

CR1A

CR1A can only be accessed in the configuration state and after the CSR has been initialized to1Ah. CR1A is directly

connected to SCE Register Block Three, Address 0x05 in the CIRCC2 block.

18.4.27

CR1B

CR1B can only be accessed in the configuration state and after the CSR has been initialized to 1Bh. CR1B is used to

set the CIRCC2 Half Duplex Turnaround Delay Time for the CIRCC2 port. This value is 0 to 25.5msec in 100µsec incre-

ments.

The CIRCC2 block includes an 8 bit IR Half Duplex Time-out register in SCE Register Block 5, Address 1 that interacts

with configuration register CR1B. These two registers behave like the other CIRCC2 Legacy controls where either

source uniformly updates the value of both registers when either register is explicitly written using IOW or following a

device-level POR. CIRCC2 software resets do not affect these registers.

The IR Half Duplex Time-out is programmable from 0 to 25.5mS in 100

S increments, as follows:

IR HALF DUPLEX TIME-OUT = (CR1B) x 100

S

18.4.28

CR1D

CR1D can only be accessed in the configuration state and after the CSR has been initialized to 09H. CR1D is a test

control register and all bits must be treated as Reserved.

TABLE 18-22: CR1A

CIRCC2 Software Select B

Type: R/W

Default: 0x00 on VCC POR

BIT NO.

BIT NAME

DESCRIPTION

0-7

Software Select B

These bits are directly connected to SCE Register Block Three, Address

0x06 in the CIRCC2 block.

TABLE 18-23: CR1B

CIRCC2 Half Duplex Timeout

Type: R/W

Default: 0x03 on VCC POR

BIT NO.

BIT NAME

DESCRIPTION

0-7

IR Half Duplex Time

Out

These bits are used to set the IR Half Duplex Turnaround Delay Time for

the IR port. This value is 0 to 25.5msec in 100µsec increments.

Note:

All test modes are reserved for Microchip use. Activating test mode registers may produce undesired

results.

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