SIO1007 datasheet(37/108 Pages) MICROCHIP

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DS00002020A-page 37

SIO1007

APPLICATION NOTE: To generate a Serial IRQ for the IRCC2.0 block, the ACE block must be located in a valid

Base I/O range and the OUT2 bit in the MCR register must be set to 1.

10.3

IRDA PME Wakeup

The IR Receive activity can wake up the system from a sleep state using the SIO1007 nIO_PME output. The IRRX2

pin wake event is falling edge detected.

APPLICATION NOTE: Very narrow pulses, which are rejected by the IRCC block, can generate wakeup events.

10.4

CIRCC2 Infrared Interface

The following section describes the features that are unique to the CIRCC2 block in the SIO1007. For more information,

consult the CIRCC 2.X Block Specification Revision 0.7, dated August 26, 2004.

10.4.1

CIRCC2 PIN INTERFACE

The CIRRX and CIRTX signals that are multiplexed on the GP15 and GP16 pins respectively are used to interface to

the CIRCC2 block.

APPLICATION NOTE: If CIRTX signal function is used and interfaced to a transceiver requiring duty cycle

protection, an external 5KOhm pulldown resistor should be used. In addition the an internal

45µA pullup resistor on the CIRTX pin should be disabled by clearing the the GP16 bit in

CR38 on page 82.

The CIRCC2 block has three ports that can be used to bring out the IR signals to three different pairs of pins. In the

SIO1007 implementation, only one of these ports is utilized (See Figure 10-2). This port is selected by the CIRCC2 Out-

put Mux bits, which may be programmed in the CR0A Configuration Register (see Section 18.4.11, "CR0A," on page 63)

or in the SCE Configuration Register B, which is located in the CIRCC2 Runtime Registers. The SCE Configuration Reg-

ister B is located in Register Block One of the CIRCC2 Runtime Registers, which is defined in the CIRCC 2.X Block

Specification Revision 0.7, dated August 26, 2004.

FIGURE 10-2:

CIRCC2 INFRARED INTERFACE BLOCK DIAGRAM

CIRCC2 Block

CIRTX

CIRRX

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