SIO1007 datasheet(78/108 Pages) MICROCHIP

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SIO1007

DS00002020A-page 78

 2005 - 2015 Microchip Technology Inc.

18.4.46

CR2F

CR2F can only be accessed in the configuration state and after the CSR has been initialized to 2FH. CR2F is directly

connected to SCE Register Block Three, Address 0x06 in the IRCC v2.0 block.

18.4.47

CR30

CR30 can only be accessed in the configuration state and after the CSR has been initialized to 21H. CR30 is used to

select the low byte of the base address (ADR[11:4] bits of Runtime Register Logical Device.

The Runtime Register logical device base address is initialized using the base address bits located in two configuration

registers: CR30-low byte and CR21-high byte. The Runtime Register base address can be set to 4080 locations on 16-

byte boundaries from 0000H - FFF0H.

The Runtime Register base address bits A[3:0] are decoded as 0000b. The Runtime Register block uses full 16-bit

addressing decoding. An address matching the Runtime Register base address bits A[15:4] is decoded using the spe-

cific address bits A[3:0] to target registers in Section 17.0, "Runtime Registers," on page 53.

When the activate bit in CR3A-bit1 is cleared to 0, no address decoding takes place for the Runtime Register block log-

ical device.

TABLE 18-40: CR2F

Software Select B

Type: R/W

Default: 0X00 ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

0-7

Software Select B

These bits are directly connected to SCE Register Block Three, Address

0x06 in the IRCC v2.0 block.

TABLE 18-41: CR30

Runtime Registers Block Base Address-Low Byte

Type: R/W

Default: 0X00 ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

ADR4

The bits in this register are used to program the location of the Runtime

ADR5

ADR6

ADR7

ADR8

ADR9

ADR10

ADR11

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