GXM datasheet(27/244 Pages) NSC

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Signal Definitions (Continued)

FRAME#

(PU)

C13

(PU)

s/t/s

Frame

Cycle Frame is driven by the current master to indicate the

beginning and duration of an access. FRAME# is asserted to

indicate a bus transaction is beginning. While FRAME# is

asserted, data transfers continue. When FRAME# is deasserted,

the transaction is in the final data phase.

This pin is internally connected to a 20-kohm pull-up resistor.

IRDY#

(PU)

D14

(PU)

s/t/s

Initiator Ready

Initiator Ready is asserted to indicate that the bus master is able

to complete the current data phase of the transaction. IRDY# is

used in conjunction with TRDY#. A data phase is completed on

any SYSCLK in which both IRDY# and TRDY# are sampled

asserted. During a write, IRDY# indicates valid data is present

on AD[31:0]. During a read, it indicates the master is prepared to

accept data. Wait cycles are inserted until both IRDY# and

TRDY# are asserted together.

This pin is internally connected to a 20-kohm pull-up resistor.

TRDY#

(PU)

B14

(PU)

s/t/s

Target Ready

TRDY# is asserted to indicate that the target agent is able to

complete the current data phase of the transaction. TRDY# is

used in conjunction with IRDY#. A data phase is complete on any

SYSCLK in which both TRDY# and IRDY# are sampled

asserted. During a read, TRDY# indicates that valid data is

present on AD[31:0]. During a write, it indicates the target is pre-

pared to accept data. Wait cycles are inserted until both IRDY#

and TRDY# are asserted together.

This pin is internally connected to a 20-kohm pull-up resistor.

STOP#

C11

(PU)

A15

(PU)

s/t/s

Target Stop

STOP# is asserted to indicate that the current target is request-

ing the master to stop the current transaction. This signal is used

with DEVSEL# to indicate retry, disconnect or target abort. If

STOP# is sampled active while a master, FRAME# will be deas-

serted and the cycle stopped within three SYSCLK cycles. As an

input, STOP# can be asserted in the following cases. 1) If a PCI

master tries to access memory that has been locked by another

master. This condition is detected if FRAME# and LOCK# are

asserted during an address phase. 2) STOP# will also be

asserted if the PCI write buffers are full or if a previously buffered

cycle has not completed. 3) Finally, STOP# can be asserted on

read cycles that cross cache line boundaries. This is conditional

based upon the programming of bit 1 in PCI Control Function 2

This pin is internally connected to a 20-kohm pull-up resistor.

2.2.2

PCI Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No

Type

Description

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