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Revision 3.1

Signal Definitions (Continued)

2.2.2

PCI Interface Signals

Signal Name

BGA

Pin No.

SPGA

Pin No

Type

Description

AD[31:0]

Refer

to Table

2-3

Refer

to Table

2-5

I/O

Multiplexed Address and Data

Addresses and data are multiplexed on the same PCI pins. A bus

transaction consists of an address phase in the cycle in which

FRAME# is asserted followed by one or more data phases. Dur-

ing the address phase, AD[31:0] contain a physical 32-bit

address. For I/O, this is a byte address, for configuration and

memory it is a DWORD address. During data phases, AD[7:0]

contain the least significant byte (LSB) and AD[31:24] contain

the most significant byte (MSB). Write data is stable and valid

when IRDY# is asserted and read data is stable and valid when

TRDY# is asserted. Data is transferred during those SYSCLKS

where both IRDY# and TRDY# are asserted.

C/BE[3:0]#

D5,

B8,

C13,

A15

B6,

B12,

B18,

E21

I/O

Multiplexed Command and Byte Enables

Bus command and byte enables are multiplexed on the same

PCI pins. During the address phase of a transaction when

FRAME# is active, C/BE[3:0]# define the bus command. During

the data phase C/BE[3:0]# are used as byte enables. The byte

enables are valid for the entire data phase and determine which

byte lanes carry meaningful data. C/BE0# applies to byte 0

(LSB) and C/BE3# applies to byte 3 (MSB).

The command encoding and types are listed below.

0000 = Interrupt Acknowledge

0001 = Special Cycle

0010 = I/O Read

0011 = I/O Write

0100 = Reserved

0101 = Reserved

0110 = Memory Read

0111 = Memory Write

1000 = Reserved

1001 = Reserved

1010 = Configuration Read

1011 = Configuration Write

1100 = Memory Read Multiple

1101 = Dual Address Cycle (Reserved)

1110 = Memory Read Line

1111 = Memory Write and Invalidate

PAR

B12

C17

I/O

Parity

Parity generation is required by all PCI agents: the master drives

PAR for address and write-data phases, the target drives PAR for

read-data phases. Parity is even across AD[31:0] and

C/BE[3:0]#.

For address phases, PAR is stable and valid one SYSCLK after

the address phase. It has the same timing as AD[31:0] but

delayed by one SYSCLK.

For data phases, PAR is stable and valid one SYSCLK after

either IRDY# is asserted on a write transaction or after TRDY# is

asserted on a read transaction. Once PAR is valid, it remains

valid until one SYSCLK after the completion of the data phase.

(Also see PERR#.)

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