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GXM 数据表(PDF) 81 Page - National Semiconductor (TI) |
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GXM 数据表(HTML) 81 Page - National Semiconductor (TI) |
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81 / 244 page ![]() Revision 3.1 81 www.national.com Processor Programming (Continued) Table 3-36. SMM Memory Space Header Description Name Description Size DR7 Debug Register 7: The contents of Debug Register 7. 4 Bytes EFLAGS Extended FLAGS Register: The contents of Extended FLAGS Register. 4 Bytes CR0 Control Register 0: The contents of Control Register 0. 4 Bytes Current IP Current Instruction Pointer: The address of the instruction executed prior to servicing SMM interrupt. 4Bytes Next IP Next Instruction Pointer: The address of the next instruction that will be executed after exiting SMM. 4Bytes CS Selector Code Segment Selector: Code segment register selector for the current code segment. 2 Bytes CS Descriptor Code Segment Descriptor: Encoded descriptor bits for the current code segment. 8 Bytes N Nested SMI Status: Flag that determines whether an SMI occurred during SMM (i.e., nested) 1 Bit V SoftVGA SMI Status: SMI was generated by an access to VGA region. 1 Bit X External SMI Status: If = 1: SMI generated by external SMI# pin If = 0: SMI internally generated by Internal Bus Interface Unit. 1Bit M Memory or I/O Access: 0 = I/O access; 1 = Memory access. 1 Bit H Halt Status: Indicates that the processor was in a halt or shutdown prior to servicing the SMM interrupt. 1Bit S Software SMM Entry Indicator: If = 1: Current SMM is the result of an SMINT instruction. If = 0: Current SMM is not the result of an SMINT instruction. 1Bit P REP INSx/OUTSx Indicator: If = 1: Current instruction has a REP prefix. If = 0: Current instruction does not have a REP prefix. 1Bit I IN, INSx, OUT, or OUTSx Indicator: If = 1: Current instruction performed is an I/O WRITE. If = 0: Current instruction performed is an I/O READ. 1Bit C CS Writable: Code Segment Writable If = 1: CS is writable If = 0: CS is not writable 1Bit I/O Data Size Indicates size of data for the trapped I/O cycle: 01h = byte 03h = word 0Fh = DWORD 2Bytes I/O Address Processor port used for the trapped I/O cycle. 2Bytes I/O or Memory Data Data associated with the trapped I/O or memory cycleS. 4Bytes Restored ESI or EDI Restored ESI or EDI Value: Used when it is necessary to repeat a REP OUTSx or REP INSx instruction when one of the I/O cycles caused an SMI# trap. 4Bytes Memory Address Physical address of the operation that caused the SMI. 4Bytes Note: INSx = INS, INSB, INSW or INSD instruction. OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction. |
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