GXM datasheet(59/244 Pages) NSC

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Processor Programming (Continued)

3.3.3

Model Specific Register Set

The Model Specific Register (MSR) Set is used to monitor

the performance of the processor or a specific component

within the processor.

A MSR can be read using the RDMSR instruction, opcode

0F32h. During a MSR read, the contents of the particular

MSR, specified by the ECX Register, is loaded into the

EDX:EAX Registers.

A MSR can be written using the WRMSR instruction,

opcode 0F30h. During a MSR write, the contents of

EX:EAX are loaded into the MSR specified in the ECX

The RDMSR and WRMSR instructions are privileged

instructions.

The GXm processor contains one 64-bit Model Specific

3.3.4

Time Stamp Counter

The processor contains a model specific register (MSR)

called the Time Stamp Counter (TSC). The TSC,

(MSR[10]), is a 64-bit counter that counts the internal

CPU clock cycles since the last reset. The TSC uses a

continuous CPU core clock and will continue to count

clock cycles even when the processor is in suspend or

shutdown mode.

The TSC is read using a RDMSR instruction, opcode 0F

32h, with the ECX register set to 10h. During a TSC read,

the contents of the TSC is loaded into the EDX:EAX regis-

ters.

The TSC is written to using a WRMSR instruction, opcode

0F 30h with the ECX register set to 10h. During a TSC

write, the contents of EX:EAX are loaded into the TSC.

The RDMSR and WRMSR instructions are privileged

instructions.

In addition, theTSC canbereadusing theRDTSC

instruction, opcode 0F 31h. The RDTSC instruction loads

the contents of the TSC into EDX:EAX. The use of the

RDTSC instruction is restricted by the TSC flag (bit 2) in

the CR4 register (refer to Tables 3-6 and 3-7 on pages 45

and 45 for CR4 register information). When the TSC bit =

0, the RDTSC instruction can be executed at any privilege

level. When the TSC bit = 1, the RDTSC instruction can

only be executed at privilege level 0.

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