GXM datasheet(47/244 Pages) NSC

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Processor Programming (Continued)

3.3.2.2

Configuration Registers

The configuration registers listed in Table 3-9 are CPU

registers and are selected by register index numbers. The

registers are accessed through I/O memory locations 22h

and 23h. Registers are selected for access by writing an

index number to I/O Port 22h using an OUT instruction

prior to transferring data through I/O Port 23h.

Each data transfer through I/O Port 23h must be preceded

by a register index selection through I/O Port 22h; other-

wise, subsequent I/O Port 23h operations are directed off-

chip and produce external I/O cycles.

If MAPEN, bit 4 of CCR3 (Index C3h[4]) = 0, external I/O

cycles occur if the register index number is outside the

range C0h-CFh, FEh, and FFh. The MAPEN bit should

remain 0 during normal operation to allow system regis-

ters located at I/O Port 22h to be accessed.

Table 3-9. Configuration Register Summary

Index

Type

Name

Access

Controlled By*

Default

Value

Reference

(Bit Formats)

C1h

R/W

CCR1 — Configuration Control 1

SMI_LOCK

00h

Table 3-11 on page 49

C2h

R/W

CCR2 — Configuration Control 2

00h

Table 3-11 on page 49

C3h

R/W

CCR3 — Configuration Control 3

SMI_LOCK

00h

Table 3-11 on page 49

E8h

R/W

CCR4 — Configuration Control 4

MAPEN

85h

Table 3-11 on page 50

EBh

R/W

CCR7 — Configuration Control 7

00h

Table 3-11 on page 50

20h

R/W

PCR — Performance Control

MAPEN

07h

Table 3-11 on page 50

B0h

R/W

SMHR0 — SMM Header Address 0

MAPEN

xxh

Table 3-11 on page 50

B1h

R/W

SMHR1 — SMM Header Address 1

MAPEN

xxh

Table 3-11 on page 50

B2h

R/W

SMHR2 — SMM Header Address 2

MAPEN

xxh

Table 3-11 on page 50

B3h

R/W

SMHR3 — SMM Header Address 3

MAPEN

xxh

Table 3-11 on page 50

B8h

R/W

GCR — Graphics Control Register

MAPEN

00h

Table 4-1 on page 92

B9h

VGACTL — VGA Control Register

00h

Table 5-5 on page 173

BAh-

BDh

VGAM0 — VGA Mask Register

00h

Table 5-5 on page 173

CDh

R/W

SMAR0 — SMM Address 0

SMI_LOCK

00h

Table 3-11 on page 51

CEh

R/W

SMAR1 — SMM Address 1

SMI_LOCK

00h

Table 3-11 on page 51

CFh

R/W

SMAR2 — SMM Address 2

SMI_LOCK

00h

Table 3-11 on page 51

FEh

DIR0 — Device ID 0

4xh

Table 3-11 on page 51

FFh

DIR1 — Device ID 1

xxh

Table 3-11 on page 51

Note:

*MAPEN = Index C3h[4] (CCR3) and SMI_LOCK = Index C3h[0] (CCR3).

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