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Processor Programming (Continued)

3.2

INSTRUCTION SET OVERVIEW

The GXm processor instruction set can be divided into

nine types of operations:

• Arithmetic

• Bit Manipulation

• Shift/Rotate

• String Manipulation

• Control Transfer

•Data Transfer

• Floating Point

• High-Level Language Support

• Operating System Support

GXm processor instructions operate on as few as zero

operands and as many as three operands. An NOP

instruction (no operation) is an example of a zero-operand

instruction. Two-operand instructions allow the specifica-

tion of an explicit source and destination pair as part of

the instruction. These two-operand instructions can be

divided into ten groups according to operand types:

• Register to Register

• Register to Memory

• Memory to Register

• Memory to Memory

•Register to I/O

• I/O to Register

• Memory to I/O

• I/O to Memory

• Immediate Data to Register

• Immediate Data to Memory

An operand can beheldinthe instructionitself(as in the

case of an immediate operand), in one of the processor’s

registers or I/O ports, or in memory. An immediate oper-

and is fetched as part of the opcode for the instruction.

Operand lengths of 8, 16, 32 or 48 bits are supported as

well as 64 or 80 bits associated with floating-point instruc-

tions. Operand lengths of 8 or 32 bits are generally used

when executing code written for 386- or 486-class (32-bit

code) processors. Operand lengths of 8 or 16 bits are

generally used when executing existing 8086 or 80286

code (16-bit code). The default length of an operand can

be overridden by placing one or more instruction prefixes

in front of the opcode. For example, the use of prefixes

allows a 32-bit operand to be used with 16-bit code or a

16-bit operand to be used with 32-bit code.

Section 9.1 “General Instruction Set Format” on page 202

contains the clock count table that lists each instruction in

the CPU instructionset.Includedinthe tableare the

associated opcodes, execution clock counts, and effects

on the EFLAGS register.

3.2.1

Lock Prefix

The LOCK prefix may be placed before certain instruc-

tions that read, modify, then write back to memory. The

PCI will not be granted access in the middle of locked

instructions. The LOCK prefix can be used with the follow-

ing instructions only when the result is a write operation to

memory.

• Bit Test Instructions (BTS, BTR, BTC)

• Exchange Instructions (XADD, XCHG, CMPXCHG)

• One-Operand Arithmetic and Logical Instructions

(DEC, INC, NEG, NOT)

• Two-Operand Arithmetic and Logical Instructions

(ADC, ADD, AND, OR, SBB, SUB, XOR).

An invalid opcode exception is generated if the LOCK pre-

fix is used with any other instruction or with one of the

instructions above when no write operation to memory

occurs (for example, when the destination is a register).

SMAR1

SMM Address 1

00h

See Table 3-11 on page 50 for bit definitions.

SMAR2

SMM Address 2 / SMAR Size

00h

See Table 3-11 on page 50 for bit definitions.

DIR0

Device Identification 0

4xh

Device ID and reads back initial CPU clock-speed set-

ting. See Table 3-11 on page 51 for bit definitions.

DIR1

Device Identification 1

xxh

Stepping and Revision ID (RO). See Table 3-11 on

page 51 for bit definitions.

DR7

Debug Register 7

00000400h

See Table 3-13 on page 53 for bit definitions.

Note: x = Undefined value

Table 3-1. Initialized Core Register Controls (Continued)

Initialized Contents

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