GXM datasheet(52/244 Pages) NSC

52 / 244 page

www.national.com

Revision 3.1

Processor Programming (Continued)

3.3.2.3

Debug Registers

Six debug registers (DR0-DR3, DR6 and DR7) support

debugging on the GXm processor. Memory addresses

loaded in the debug registers, referred to as “breakpoints,”

generate a debug exception when a memory access of

thespecifiedtypeoccursto the specifiedaddress.A

breakpoint can be specified for a particular kind of mem-

ory access such as a read or write operation. Code and

data breakpoints can also be set allowing debug excep-

tions to occur whenever a given data access (read or write

operation) or code access (execute) occurs. The size of

the debug target can be set to 1, 2, or 4 bytes. The debug

registers are accessed through MOV instructions that can

be executed only at privilege level 0 (real mode is always

privilege level 0).

The Debug Address Registers (DR0-DR3) each contain

the linear address for one of four possible breakpoints.

Each breakpoint is further specified by bits in the Debug

Control Register (DR7). For each breakpoint address in

DR0-DR3, there are corresponding fields L, R/W, and

LEN in DR7 that specify the type of memory access asso-

ciated with the breakpoint.

The R/W field can be used to specify instruction execution

as well as data access breakpoints. Instruction execution

breakpoints are always taken before execution of the

instruction that matches the breakpoint. The Debug Reg-

isters are mapped in Table 3-12

Table 3-12. Debug Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

8765

43210

DR7 Register

Debug Control Register 7 (R/W)

LEN3

R/W3

LEN2

R/W2

LEN1

R/W1

LEN0

R/W0

0010

DR6 Register

Debug Status Register 6 (RO)

00000

0000

00000

01111

1111

B3 B2 B1 B0

DR3 Register‘

Debug Address Register 3 (R/W))

Breakpoint 3 Linear Address

DR2 Register

Debug Address Register 2 (R/W)

Breakpoint 2 Linear Address

DR1 Register

Debug Address Register 1 (R/W)

Breakpoint 1 Linear Address

DR0 Register

Debug Address Register 0 (R/W)

Breakpoint 0 Linear Address

Note: All bits marked as 0 or 1 are reserved and should not be modified.

GXM 数据表(PDF) 52 Page - National Semiconductor (TI)

GXM 数据表(HTML) 52 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载