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Processor Programming (Continued)

3.11.7 SMM Memory Space

SMM memory space is defined by specifying the base

address and size of the SMM memory space in the SMAR

memory space size. For example, a 32 KB SMM memory

space must be located at a 32 KB address boundary. The

memory space size can range from 4 KB to 32 MB. Execu-

tion of the interrupt begins at the base of the SMM memory

space.

SMM memory space accesses are always cacheable,

which allows SMM routines to run faster.

3.11.8 SMI Generation

Virtualization software depends on processor-specific

hardware to generate SMI interrupts for each memory or

I/O access to the device being implemented. The GXm

processor implements SMI generation for VGA accesses.

Memory write operations in regions A0000h to AFFFFh,

B0000h to B7FFFh, and B8000h to BFFFFh generate an

SMI.

Memory reads are not trapped by the GXm processor.

The GXm processor traps I/O addresses for VGA in the

following regions: 3B0h to 3BFh, 3C0h to 3CFh, and 3D0h

to 3DFh. Memory-write trapping is performed during

instruction decode in the processor core. I/O read and

write trapping is implemented in the Internal Bus Interface

Unit of the GXm processor.

The SMI-generation hardware requires two additional

configuration registers to control and mask SMI interrupts

in the VGA memory space: VGACTL and VGAM. The

VGACTL register has a control bit for each address range

shown above. The VGAM register has 32 bits that can

selectively disable 2 KB regions within the VGA memory.

The VGAM applies only to the A0000h-to-AFFFFh region.

If this region is not enabled in VGA_CTL, then the con-

tents of VGAM is ignored. The purpose of VGAM is to pre-

vent SMI from occurring when non-displayed VGA

memory is accessed. This is an enhancement which

improves performance for double-buffered applications.

Theformatofeachregister isshowninChapter4 of this

document.

3.11.9 SMI Service Routine Execution

Upon entry into SMM, after the SMM header has been

saved, the CR0, EFLAGS, and DR7 registers are set to

their reset values. The Code Segment (CS) register is

loaded with the base, as defined by the SMAR register,

and a limit of 4 GBytes. The SMI service routine then

begins execution at the SMM base address in real mode.

The programmer must save the value of any registers that

may be changed by the SMI service routine. For data

accesses immediately after entering the SMI service rou-

tine, the programmer must use CS as a segment override.

I/O port access is possible during the routine but care

must be taken to save registers modified by the I/O

instructions. Before using a segment register, the register

and the register’s descriptor cache contents should be saved

using the SVDC instruction.

Hardware interrupts, INTRs and NMIs, may be serviced

duringanSMI serviceroutine. If interrupts aretobeser-

viced while executing in the SMM memory space, the

SMM memory space must be within the address range of

0 to 1 MB to guarantee proper return to the SMI service

routine after handling the interrupt.

INTRs are automatically disabled when entering SMM

since the IF flag (EFLAGS register, bit 9) is set to its reset

value. Once in SMM, the INTR can be enabled by setting

the IF flag. An NMI event in SMM can be enabled by set-

ting NMI_EN high in the CCR3 register (Index C3h[1]). If

NMI is not enabled while in SMM, the CPU latches one

NMI event and services the interrupt after NMI has been

enabled or after exiting SMM through the RSM instruction.

The processor is always in real mode in SMM, but it may

exit to either real or protected mode depending on its

state when SMM was initiated. The IDT (Interrupt Descrip-

tor Table) indicates which state it will exit to.

Within the SMI service routine, protected mode may be

entered and exited as required, and real or protected

mode device drivers may be called.

To exit the SMI service routine, a Resume (RSM) instruc-

tion, rather than an IRET, is executed. The RSM instruc-

tion causes the GXm processor core to restore the CPU

state using the SMM header information and resume exe-

cution at the interrupted point. If the full CPU state was

saved by the programmer, the stored values should be

reloaded before executing the RSM instruction using the

MOV, RSDC, RSLDT and RSTS instructions.

3.11.9.1 SMI Nesting

The SMI mechanism supports nesting of SMI interrupts

through the SMI handler, the SMI_NEST bit in CCR4[6]

(Index E8h), and the Nested SMI Status bit (bit N in the

SMM header, see Table on page 80). Nesting is an impor-

tant capability in allowing high-priority events, such as

audio virtualization, to interrupt lower-priority SMI code for

VGA virtualization or power management. SMI_NEST

controls whether SMI interrupts can occur during SMM.

SMI handlers can optionally set SMI_NEST high to allow

higher-priority SMI interrupts while handling the current

event.

The SMI handler is responsible for managing the SMI

header data for nested SMI interrupts. The SMI header

must be saved before SMI_NEST is set high, and

SMI_NEST must be cleared and its header information

restored before an RSM instruction is executed.

The Nested SMI Status bit has been added to the SMM

header to show whether the current SMI is nested. The

processor sets Nested SMI Status high if the processor

was in SMM when the SMI was taken. The processor

uses Nested SMI Status on exit to determine whether the

processor should stay in SMM.

When SMI nesting is disabled, the processor holds off

external SMI interrupts until the currently executing SMM

code exits. When SMI nesting is enabled, the processor

can proceed with the SMI. The SMI handler will guarantee

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