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Integrated Functions (Continued)

4.1.2

Control Registers

The control registers for the GXm processor use 32 KB of

the memory map, starting at GX_BASE+8000h (see Fig-

ure 4-2 on page 93). This area is divided into internal bus

interface unit, graphics pipeline, display controller, mem-

ory controller, and power management sections:

• The internal bus interface unit maps 100h locations

starting at GX_BASE+8000h.

• The graphics pipeline maps 200h locations starting at

GX_BASE+8100h.

• The display controller maps 100h locations starting at

GX_BASE+8300h.

• The memory controller maps 100h locations starting at

GX_BASE+8400h

• GX_BASE+8500h-8FFFh is dedicated to power

management registers for the serial packet transmis-

sion control, the user-defined power management

address space, Suspend Refresh, and SMI status for

Suspend/Resume.

The register descriptions are contained in the individual

subsections of this chapter. Accesses to undefined regis-

ters in the GXm processor control register space will not

cause a hardware error.

4.1.3

Graphics Memory

The GXm processor’s graphics memory is mapped into 8

MB starting at GX_BASE+800000h. This area includes

the frame buffer memory and storage for internal display

controller state. The frame buffer is a linear map whose

size depends on the current resolution setup in the mem-

ory controller. Frame buffer scan lines are not contiguous

in many resolutions, so software that renders to the frame

buffer must use a skip count to advance between scan

lines. The display controller uses the graphics memory

that lies between scan lines for internal state. For this rea-

son, accessing graphics memory between the end of a

scan line and the start of another can cause display prob-

lems. The skip count for all supported resolutions is

shownin Table4-2.

Graphics memory is allocated from system DRAM by the

system BIOS. The graphics memory size is programmed

by setting the graphics memory base address in the mem-

ory controller. Display drivers communicate with system

BIOS about resolution changes, to ensure that the correct

amount of graphics memory is allocated. When a graphics

resolution change requires an increased amount of graph-

ics memory, the system must be rebooted! Thereasonfor

this restriction is that no mechanism exists to recover sys-

tem DRAM from the operating system without rebooting.

Table 4-2. Display Resolution Skip Counts

Screen

Resolution

Pixel

Depth

Skip

Count

640x480

8 bits

1024

640x480

16 bits

2048

800x600

8 bits

1024

800x600

16 bits

2048

1024x768

8 bits

1024

1024x768

16 bits

2048

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