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Revision 3.1

Integrated Functions (Continued)

4.1

INTEGRATED FUNCTIONS PROGRAMMING INTERFACE

The GXm processor performs mapping for the dedicated

cache, graphics pipeline, display controller, memory con-

troller, and graphics memory, including the frame buffer. It

maps these to high memory addresses or GXm processor

memory space. The base address for these is controlled

by the Graphics Configuration Register (GCR, Index B8h),

which specifies address bits [31:30] in physical memory.

Figure 4-2 on page 93 shows the address map for the

GXm processor. When accessing the GXm processor

memory space, address bits [29:24] must be zero. This

allows the GXm processor a linear address space with a

total of 16 MB. Address bit 23 divides this space into 8 MB

for control (bit 23 = 0) and 8 MB for graphics memory (bit

23 = 1). In control space, bits [22:16] are not decoded, so

the programmer should set them to zero. Address bit 15

divides the remaining 64 KB address space into scratch-

pad RAM and PCI access (bit 15 = 0) and control regis-

ters (bit 15 = 1).

Device drivers must be responsible for performing physi-

cal-to-virtual memory-address translation, including allo-

cation of selectors that point to the GXm processor. The

processor may be accessed in protected mode by creat-

ing a selector with the physical address shown in Table 4-

1, and a limit of 16 MB. A selector with a 64 KB limit is

large enough to access all of the GXm processor’s regis-

ters and scratchpad RAM.

4.1.1

Graphics Control Register

The GXm processor incorporates graphics functions that

require registers to implement and control them. Most of

these registers are memory mapped and physically

located in the logical units they control. The mapping of

these units is controlled by this configuration register. The

Graphics Control Register (GCR, Index B8h) is I/O-

mapped because it must be accessed before memory

mapping can be enabled. Refer to Section 3.3.2.2 “Con-

figuration Registers” on page 47 for information on how to

access this register.

Table 4-1. GCR Register

Bit

Name

Description

Index B8h

GCR Register (R/W)

Default Value = 00h

7:4

RSVD

Reserved: Set to 0.

3:2

Scratchpad Size: Specifies the size of the scratchpad cache.

00 = 0 KB

01 = 2 KB

10 = 3 KB

11 = 4 KB

1:0

GXm Base Address: Specifies the physical address for the base (GX_BASE) of the scratchpad RAM, the

graphics memory (frame buffer, compression buffer, etc.) and the other memory mapped registers.

00 = Scratchpad RAM, Graphics Subsystem, and memory-mapped configuration registers are disabled.

01 = Scratchpad RAM and control registers start at GX_BASE = 40000000h.

10 = Scratchpad RAM and control registers start at GX_BASE = 80000000h.

11 = Scratchpad RAM and control registers start at GX_BASE = C0000000h.

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