GXM datasheet(38/244 Pages) NSC

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Revision 3.1

3.0

Processor Programming

This section describes the internal operations of the

Geode GXm processor from a programmer’s point of view.

It includes a description of the traditional “core” process-

ing and FPU operations. The integrated function registers

are described at the end of this chapter.

The primary register sets within the processor core

include:

• Application Register Set

• System Register Set

• Model Specific Register Set

• Floating Point Unit Register Set.

The initialization of the major registers within in core are

shownin Table3-1.

Theintegratedfunctionsetsare locatedinmainmemory

space and include:

• Internal Bus Interface Unit Register Set

• Graphics Pipeline Register Set

• Display Controller Register Set

• Memory Controller Register Set

• Power Management Register Set

3.1

CORE PROCESSOR INITIALIZATION

The GXm processor is initialized when the RESET signal

is asserted. The processor is placed in real mode and the

registers listed in Table 3-1 are set to their initialized val-

ues. RESET invalidates and disables the CPU cache, and

turns off paging. When RESET is asserted, the CPU ter-

minates all local bus activity and all internal execution.

During the entire time that RESET is asserted, the inter-

nal pipeline is flushed and no instruction execution or bus

activity occurs.

Approximately 150 to 250 external clock cycles after

RESET is deasserted, the processor begins executing

instructions at the top of physical memory (address loca-

tion FFFFFFF0h). The actual time depends on the clock

scaling in use. Also, an additional 220 clock cycles are

needed when self-test is requested.

Typically, an intersegment jump is placed at FFFFFFF0h.

This instruction will force the processor to begin execution

in the lowest 1 MB of address space.

Thefollowing table, Table3-1,lists thecoreregisters and

illustrates how they are initialized.

Table 3-1. Initialized Core Register Controls

Initialized Contents

Comments

EAX

Accumulator

xxxxxxxxh

00000000h indicates self-test passed.

EBX

Base

xxxxxxxxh

ECX

Count

xxxxxxxxh

EDX

Data

xxxx 04 [DIR0]h

DIR0 = Device ID

EBP

Base Pointer

xxxxxxxxh

ESI

Source Index

xxxxxxxxh

EDI

Destination Index

xxxxxxxxh

ESP

Stack Pointer

xxxxxxxxh

EFLAGS

Extended FLAGS

00000002h

See Table 3-4 on page 43 for bit definitions.

EIP

Instruction Pointer

0000FFF0h

Extra Segment

0000h