GXM datasheet(10/244 Pages) NSC

10 / 244 page

www.national.com

Revision 3.1

Architecture Overview (Continued)

1.5.2

Display Controller

The display port is a direct interface to the CS5530 which

drives a TFT flat panel display, LCD panel, or a CRT dis-

play.

The display controller (video generator) retrieves image

data from the frame buffer region of memory, performs a

color-look-up if required, inserts the cursor overlay into

the pixel stream, generates display timing, and formats

the pixel data for output to a variety of display devices.

The display controller contains Display Compression

Technology (DCT) that allows the GXm processor to

refresh the display from a compressed copy of the frame

buffer. DCT typically decreases the screen-refresh band-

width requirement by a factor of 15 to 20, further minimiz-

ing bandwidth contention.

1.5.3

XpressRAM Memory Subsystem

The memory controller drives a 64-bit SDRAM port

directly. The SDRAM memory array contains both the

main system memory and the graphics frame buffer. Up to

four module banks of SDRAM are supported. Each mod-

ule bank will have two or four component banks depend-

ing on the memory size and organization. The maximum

configuration is four module banks with four component

banks providing a total of 16 open banks. The maximum

memory size is 1 GB.

The memory controller handles multiple requests for

memory data from the GXm processor, the graphics

accelerator and the display controller. The memory con-

troller contains extensive buffering logic that helps mini-

mize contention for memory bandwidth between graphics

and CPU requests. The memory controller cooperates

with the internal bus controller to determine the cacheabil-

ity of all memory references.

1.5.4

PCI Controller

The GXm processor incorporates a full-function PCI inter-

face module that includes the PCI arbiter. All accesses to

external I/O devices are sent over the PCI bus, although

most memory accesses are serviced by the SDRAM con-

troller. The Internal Bus Interface Unit contains address

mapping logic that determines if memory accesses are

targeted for the SDRAM or for the PCI bus.

GXM 数据表(PDF) 10 Page - National Semiconductor (TI)

GXM 数据表(HTML) 10 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载