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Processor Programming (Continued)

3.13.3 Privilege Level Transfers

A task’s CPL can be changed only through intersegment

control transfers using gates or task switches to a code

segment with a different privilege level. Control transfers

result from exception and interrupt servicing and from

execution of the CALL, JMP, INT, IRET and RET instruc-

tions.

There are five types of control transfers that are summa-

rized in Table 3-38. Control transfers can be made only

when the operation causing the control transfer references

the correct descriptor type. Any violation of these descriptor

usage rules causes a general protection fault.

Any control transfer that changes the CPL within a task

results in a change of stack. The initial values for the stack

segment (SS) and stack pointer (ESP) for privilege levels

0, 1, and 2 are stored in the TSS. During a JMP or CALL

control transfer, the SS and ESP are loaded with the new

stack pointer and the previous stack pointer is saved on

the new stack. When returning to the original privilege

level, the RET or IRET instruction restores the SS and

ESP of the less-privileged stack.

3.13.3.1 Gates

Gate descriptors described in Section 3.7.5 “Gate

Descriptors” on page 69, provide protection for privilege

transfers among executable segments. Gates are used to

transition to routines of the same or a more privileged

level. Call gates, interrupt gates and trap gates are used for

privilege transfers within a task. Task gates are used to

transfer between tasks.

Gates conform to the standard rules of privilege. In other

words, gates can be accessed by a task if the effective

privilege level (EPL) is the same or more privileged than

the gate descriptor’s privilege level (DPL).

3.13.4 Initialization and Transition to Protected Mode

The GXm processor core switches to real mode immedi-

ately after RESET. While operating in real mode, the sys-

tem tables and registers should be initialized. The GDTR

and IDTR must point to a valid GDT and IDT, respectively. The

size of the IDT should be at least 256 bytes, and the GDT

must contain descriptors that describe the initial code and

data segments.

Theprocessor canbeplacedinprotected mode by setting

the PE bit (CR0 register bit 0). After enabling protected

mode, the CS register should be loaded and the instruc-

tion decode queue should be flushed by executing an

intersegment JMP. Finally, all data segment registers

should be initialized with appropriate selector values.

Table 3-38. Descriptor Types Used for Control Transfer

Type of Control Transfer

Operation Types

Descriptor

Referenced

Descriptor

Table

Intersegment within the same privilege

level.

JMP, CALL, RET, IRET*

Code Segment

GDT or LDT

Intersegment to the same or a more

privileged level. Interrupt within task

(could change CPL level).

CALL

Gate Call

GDT or LDT

Interrupt Instruction, Exception,

External Interrupt

Trap or Interrupt Gate

IDT

Intersegment to a less privileged level

(changes task CPL).

RET, IRET*

Code Segment

GDT or LDT

Task Switch via TSS

CALL, JMP

Task State Segment

GDT

Task Switch via Task Gate

CALL, JMP

Task Gate

GDT or LDT

IRET**, Interrupt Instruction,

Exception, External Interrupt

Task Gate

IDT

Note:

*NT = 0 (Nested Task bit in EFLAGS, bit 14)

**NT =1 (Nested Task bit in EFLAGS, bit 14)

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