GXM datasheet(95/244 Pages) NSC

95 / 244 page

Revision 3.1

www.national.com

Integrated Functions (Continued)

4.1.4

L1 Cache Controller

The GXm processor contains an on-board 16 KB unified

data/instruction L1 cache. It operates in write-back mode.

Since the memory controller is also on-board, the L1

cache requires no external logic to maintain coherency. All

DMA cycles automatically snoop the L1 cache. For

improved graphics performance, part of the L1 cache

operates as a scratchpad RAM to be used by the graphics

pipeline as a BLT Buffer.

The CD bit (Cache Disable, bit 30) in CR0 globally con-

trols the operating mode of the L1 cache. LCD and LWT,

Local Cache Disable and Local Write-through bits in the

Translation Lookaside Buffer, control the mode on a page-

by-page basis. Additionally, memory configuration control

can specify certain memory regions as non-cacheable.

If the cache is disabled, no further cache line fills occur.

However, data already present in the cache continues to

be used. For the cache to be completely disabled, the

cache must be invalidated with a WBINVD instruction

after the cache has been disabled.

Write-back caching improves performance by relieving

congestion on slower external buses. With four dirty bits,

the cache marks dirty locations on a double-word basis.

This further reduces the number of double-word bus write

operations needed during a replacement or flush opera-

tion.

The GXm processor will cache SMM regions. This speeds

up system management overhead to allow for hardware

emulation such as VGA.

The cache of the GXm processor provides the ability to

redefine 2KB, 3KB, or 4KB of the L1 cacheto be

scratchpad memory. The scratchpad area is memory

mapped to the upper memory region defined by the GCR

RAMwillalwaysbetrueand the scratchpadRAM loca-

tions will never be flushed to memory. The scratchpad

RAM serves as a general purpose high speed RAM and

as a BLT buffer for the graphics pipeline. Incrementing

BLT buffer address registers have been added to enable

the graphics pipeline to access this memory as a BLT

buffer. A 16-byte line buffer dedicated to the graphics

pipeline accesses has been added to minimize graphics

interference with normal CPU operation.

Table 4-3 summarizes the registers contained in the L1

cache. These registers do not have default values and

must be initialized before use. Table 4-4 on page 96 gives

the register/bit formats.

Table 4-3. L1 Cache BitBLT Register Summary

Mnemonic Name

Function

L1_BB0_BASE

L1 Cache BitBLT 0 Base Address

Contains the address offset to the first byte of BLT Buffer 0 in the scratch-

pad memory.

L1_BB0_POINTER

L1 Cache BitBLT 0 Pointer

Contains the address offset to the current line of BLT Buffer 0 in the

scratchpad memory.

L1_BB1_BASE

L1 Cache BitBLT 1 Base Address

Contains the offset to the first byte of BLT Buffer 1 in the scratchpad mem-

ory.

L1_BB1_POINTER

L1 Cache BitBLT 1 Pointer

Contains the address offset to the current line of BLT Buffer 1 in the

scratchpad memory.

Note:

For information on accessing these registers, refer to Section 4.1.6 “CPU_READ/CPU_WRITE Instructions”

on page 99.

GXM 数据表(PDF) 95 Page - National Semiconductor (TI)

GXM 数据表(HTML) 95 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载